[coreboot-gerrit] New patch to review for coreboot: mainboard/gigabyte: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Oct 7 12:50:04 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16914
-gerrit
commit 8e8b83f47e086b5e48ced76e9a7a00bce7dd75a6
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Oct 7 12:48:42 2016 +0200
mainboard/gigabyte: Use C89 comments style & remove commented code
Change-Id: Ib71aa8ff5ebe709b8884aeaabef6e4aa1a401d6d
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c | 2 +-
src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c | 4 +-
src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 94 ++++-------------------
src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c | 2 +-
src/mainboard/gigabyte/ga-b75m-d3v/romstage.c | 24 +++---
src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 4 +-
src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 6 +-
src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c | 32 +++-----
src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c | 22 +++---
src/mainboard/gigabyte/ga_2761gxdk/mptable.c | 18 ++---
src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 6 +-
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 23 +++---
src/mainboard/gigabyte/m57sli/fanctl.c | 4 -
src/mainboard/gigabyte/m57sli/get_bus_conf.c | 32 +++-----
src/mainboard/gigabyte/m57sli/irq_tables.c | 6 +-
src/mainboard/gigabyte/m57sli/mptable.c | 2 +-
src/mainboard/gigabyte/m57sli/resourcemap.c | 6 +-
src/mainboard/gigabyte/m57sli/romstage.c | 39 +++-------
src/mainboard/gigabyte/ma785gm/mainboard.c | 3 +-
src/mainboard/gigabyte/ma785gm/resourcemap.c | 12 +--
src/mainboard/gigabyte/ma785gm/romstage.c | 25 ++----
src/mainboard/gigabyte/ma785gmt/mainboard.c | 20 +----
src/mainboard/gigabyte/ma785gmt/resourcemap.c | 12 +--
src/mainboard/gigabyte/ma785gmt/romstage.c | 25 ++----
src/mainboard/gigabyte/ma78gm/mainboard.c | 1 -
src/mainboard/gigabyte/ma78gm/resourcemap.c | 12 +--
src/mainboard/gigabyte/ma78gm/romstage.c | 25 ++----
27 files changed, 129 insertions(+), 332 deletions(-)
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
index 978ce55..2fa4f6f 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/acpi_tables.c
@@ -52,7 +52,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- // the lid is open by default.
+ /* the lid is open by default. */
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
index 7b1c506..7dd0a09 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/mainboard.c
@@ -69,8 +69,8 @@ static void mainboard_init(device_t dev)
RCBA32(0x3848) = 0x0000000e;
}
-// mainboard_enable is executed as first thing after
-// enumerate_buses().
+/* mainboard_enable is executed as first thing after */
+/* enumerate_buses(). */
static void mainboard_enable(device_t dev)
{
diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
index 06fee7e..cc6c196 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c
@@ -36,19 +36,19 @@
static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
{
/* GPIO SIO settings */
- ite_reg_write(dev, 0xEF, 0x7E); // magic
-
- ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
- ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
- ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
- ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
- ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
- ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
- ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
- ite_reg_write(dev, 0xe9, 0x27); // bus select disable
- ite_reg_write(dev, 0xf0, 0x10); // ?
- ite_reg_write(dev, 0xf1, 0x42); // ?
- ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+ ite_reg_write(dev, 0xEF, 0x7E); /* magic */
+
+ ite_reg_write(dev, 0x25, 0x40); /* gpio pin function -> gp16 */
+ ite_reg_write(dev, 0x27, 0x10); /* gpio pin function -> gp34 */
+ ite_reg_write(dev, 0x2c, 0x80); /* smbus isolation on parallel port */
+ ite_reg_write(dev, 0x62, 0x0a); /* simple iobase 0xa00 */
+ ite_reg_write(dev, 0x72, 0x20); /* watchdog timeout clear! */
+ ite_reg_write(dev, 0x73, 0x00); /* watchdog timeout clear! */
+ ite_reg_write(dev, 0xcb, 0x00); /* simple io set4 direction -> in */
+ ite_reg_write(dev, 0xe9, 0x27); /* bus select disable */
+ ite_reg_write(dev, 0xf0, 0x10); /* ? */
+ ite_reg_write(dev, 0xf1, 0x42); /* ? */
+ ite_reg_write(dev, 0xf6, 0x1c); /* hardware monitor alert beep -> gp36(pin12) */
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
@@ -63,74 +63,6 @@ static void it8728f_b75md3h_disable_reboot(pnp_devfn_t dev)
void rcba_config(void)
{
-/*
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1);
- pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE + 4, 0);
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44, 0x80);
-
- outw (inw (DEFAULT_PMBASE | 0x003c) | 2, DEFAULT_PMBASE | 0x003c);
-
- RCBA32(0x3500) = 0x2000035f;
- RCBA32(0x3504) = 0x2000035f;
- RCBA32(0x3508) = 0x2000035f;
- RCBA32(0x350c) = 0x2000035f;
- RCBA32(0x3510) = 0x2000035f;
- RCBA32(0x3514) = 0x2000035f;
- RCBA32(0x3518) = 0x2000035f;
- RCBA32(0x351c) = 0x2000035f;
- RCBA32(0x3520) = 0x2000035f;
- RCBA32(0x3524) = 0x2000035f;
- RCBA32(0x3528) = 0x2000035f;
- RCBA32(0x352c) = 0x2000035f;
- RCBA32(0x3530) = 0x2000035f;
- RCBA32(0x3534) = 0x2000035f;
- RCBA32(0x3560) = 0x024c8001;
- RCBA32(0x3564) = 0x000024a3;
- RCBA32(0x3568) = 0x00040002;
- RCBA32(0x356c) = 0x01000050;
- RCBA32(0x3570) = 0x02000662;
- RCBA32(0x3574) = 0x18000f9f;
- RCBA32(0x3578) = 0x1800ff4f;
- RCBA32(0x357c) = 0x0001d530;
- RCBA32(0x35a0) = 0xc0300c03;
- RCBA32(0x35a4) = 0x00241803;
-
- pcie_write_config32 (PCI_DEV (0, 0x14, 0), 0xe4, 0x00000000);
-
- outw (0x0000, DEFAULT_PMBASE | 0x003c);
-
- RCBA32(0x2240) = 0x00330e71;
- RCBA32(0x2244) = 0x003f0eb1;
- RCBA32(0x2248) = 0x002102cd;
- RCBA32(0x224c) = 0x00f60000;
- RCBA32(0x2250) = 0x00020000;
- RCBA32(0x2254) = 0x00e3004c;
- RCBA32(0x2258) = 0x00e20bef;
- RCBA32(0x2260) = 0x003304ed;
- RCBA32(0x2278) = 0x001107c1;
- RCBA32(0x227c) = 0x001d07e9;
- RCBA32(0x2280) = 0x00e20000;
- RCBA32(0x2284) = 0x00ee0000;
- RCBA32(0x2288) = 0x005b05d3;
- RCBA32(0x2318) = 0x04b8ff2e;
- RCBA32(0x231c) = 0x03930f2e;
-// RCBA32(0x3418) = 0x1fee1fe1;
- RCBA32(0x3808) = 0x005044a3;
- RCBA32(0x3810) = 0x52410000;
- RCBA32(0x3814) = 0x0000008a;
- RCBA32(0x3818) = 0x00000006;
- RCBA32(0x381c) = 0x0000072e;
- RCBA32(0x3820) = 0x0000000a;
- RCBA32(0x3824) = 0x00000123;
- RCBA32(0x3828) = 0x00000009;
- RCBA32(0x382c) = 0x00000001;
- RCBA32(0x3834) = 0x0000061a;
- RCBA32(0x3838) = 0x00000003;
- RCBA32(0x383c) = 0x00000a76;
- RCBA32(0x3840) = 0x00000004;
- RCBA32(0x3844) = 0x0000e5e4;
- RCBA32(0x3848) = 0x0000000e;
-*/
/* Disable unused devices (board specific) */
RCBA32(FD) = 0x17ee1fe1;
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
index 978ce55..2fa4f6f 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/acpi_tables.c
@@ -52,7 +52,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs)
gnvs->s5u0 = 0;
gnvs->s5u1 = 0;
- // the lid is open by default.
+ /* the lid is open by default. */
gnvs->lids = 1;
acpi_update_thermal_table(gnvs);
diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
index 83a53d0..5a2e469 100644
--- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
+++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c
@@ -36,19 +36,19 @@
static void it8728f_b75md3v_disable_reboot(pnp_devfn_t dev)
{
/* GPIO SIO settings */
- ite_reg_write(dev, 0xEF, 0x7E); // magic
+ ite_reg_write(dev, 0xEF, 0x7E); /* magic */
- ite_reg_write(dev, 0x25, 0x40); // gpio pin function -> gp16
- ite_reg_write(dev, 0x27, 0x10); // gpio pin function -> gp34
- ite_reg_write(dev, 0x2c, 0x80); // smbus isolation on parallel port
- ite_reg_write(dev, 0x62, 0x0a); // simple iobase 0xa00
- ite_reg_write(dev, 0x72, 0x20); // watchdog timeout clear!
- ite_reg_write(dev, 0x73, 0x00); // watchdog timeout clear!
- ite_reg_write(dev, 0xcb, 0x00); // simple io set4 direction -> in
- ite_reg_write(dev, 0xe9, 0x27); // bus select disable
- ite_reg_write(dev, 0xf0, 0x10); // ?
- ite_reg_write(dev, 0xf1, 0x42); // ?
- ite_reg_write(dev, 0xf6, 0x1c); // hardware monitor alert beep -> gp36(pin12)
+ ite_reg_write(dev, 0x25, 0x40); /* gpio pin function -> gp16 */
+ ite_reg_write(dev, 0x27, 0x10); /* gpio pin function -> gp34 */
+ ite_reg_write(dev, 0x2c, 0x80); /* smbus isolation on parallel port */
+ ite_reg_write(dev, 0x62, 0x0a); /* simple iobase 0xa00 */
+ ite_reg_write(dev, 0x72, 0x20); /* watchdog timeout clear! */
+ ite_reg_write(dev, 0x73, 0x00); /* watchdog timeout clear! */
+ ite_reg_write(dev, 0xcb, 0x00); /* simple io set4 direction -> in */
+ ite_reg_write(dev, 0xe9, 0x27); /* bus select disable */
+ ite_reg_write(dev, 0xf0, 0x10); /* ? */
+ ite_reg_write(dev, 0xf1, 0x42); /* ? */
+ ite_reg_write(dev, 0xf6, 0x1c); /* hardware monitor alert beep -> gp36(pin12) */
/* EC SIO settings */
ite_reg_write(IT8728F_EC, 0xf1, 0xc0);
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
index d606582..eddca21 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c
@@ -19,8 +19,8 @@
const u32 cim_verb_data[] = {
/* coreboot specific header */
0x10ec0887,
- 0x1458a002, // Subsystem ID
- 0x0000000e, // Number of entries
+ 0x1458a002, /* Subsystem ID */
+ 0x0000000e, /* Number of entries */
/* Pin Widget Verb Table */
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
index 2503db9..e217d9c 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c
@@ -89,8 +89,8 @@ static void mb_gpio_init(void)
ite_reg_write(EC_DEV, 0xf1, 0x00);
ite_reg_write(EC_DEV, 0xf2, 0x0a);
ite_reg_write(EC_DEV, 0xf3, 0x80);
- ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
- ite_reg_write(EC_DEV, 0x30, 0x01); // Enable
+ ite_reg_write(EC_DEV, 0x70, 0x00); /* Don't use IRQ9 */
+ ite_reg_write(EC_DEV, 0x30, 0x01); /* Enable */
/* IRQ routing */
RCBA32(0x3100) = 0x00002210;
@@ -134,7 +134,7 @@ static void ich7_enable_lpc(void)
void mainboard_romstage_entry(unsigned long bist)
{
- // ch0 ch1
+ /* ch0 ch1 */
const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
/* Disable watchdog timer */
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
index 53171c2..496b916 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
@@ -27,32 +27,18 @@
#include <cpu/amd/amdk8_sysconf.h>
#include <stdlib.h>
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_sis966[8]; //1
+/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
+/*busnum is default */
+unsigned char bus_sis966[8]; /*1 */
unsigned apicid_sis966;
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+unsigned pci1234x[] = { /*Here you only need to set value in pci1234 for HT-IO that could be installed or not */
+ /*You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
};
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+unsigned hcdnx[] = { /*HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
};
static unsigned get_bus_conf_done = 0;
@@ -67,7 +53,7 @@ void get_bus_conf(void)
int i;
if (get_bus_conf_done == 1)
- return; //do it only once
+ return; /*do it only once */
get_bus_conf_done = 1;
@@ -79,7 +65,7 @@ void get_bus_conf(void)
get_sblk_pci1234();
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */
sbdn = sysconf.sbdn;
for (i = 0; i < 8; i++) {
@@ -113,7 +99,7 @@ void get_bus_conf(void)
}
}
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
index d1168a7..37a0f7e 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
@@ -45,7 +45,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
pirq_info->rfu = rfu;
}
-extern unsigned char bus_sis966[8]; //1
+extern unsigned char bus_sis966[8]; /* 1 */
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -59,7 +59,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t sum = 0;
int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
@@ -138,23 +138,23 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_DEBUG, "Setting Onboard SiS Southbridge\n");
- dev = dev_find_slot(0, PCI_DEVFN(2, 5)); // 5513 (IDE)
+ dev = dev_find_slot(0, PCI_DEVFN(2, 5)); /* 5513 (IDE) */
pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(3, 0)); // USB 1.1
+ dev = dev_find_slot(0, PCI_DEVFN(3, 0)); /* USB 1.1 */
pci_write_config8(dev, 0x3C, 0x0B);
- dev = dev_find_slot(0, PCI_DEVFN(3, 1)); // USB 1.1
+ dev = dev_find_slot(0, PCI_DEVFN(3, 1)); /* USB 1.1 */
pci_write_config8(dev, 0x3C, 0x05);
- dev = dev_find_slot(0, PCI_DEVFN(3, 3)); // USB 2.0
+ dev = dev_find_slot(0, PCI_DEVFN(3, 3)); /* USB 2.0 */
pci_write_config8(dev, 0x3C, 0x07);
- dev = dev_find_slot(0, PCI_DEVFN(4, 0)); // 191 (LAN)
+ dev = dev_find_slot(0, PCI_DEVFN(4, 0)); /* 191 (LAN) */
pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(5, 0)); // 1183 (SATA)
+ dev = dev_find_slot(0, PCI_DEVFN(5, 0)); /* 1183 (SATA) */
pci_write_config8(dev, 0x3C, 0x0B);
- dev = dev_find_slot(0, PCI_DEVFN(6, 0)); // PCI-E
+ dev = dev_find_slot(0, PCI_DEVFN(6, 0)); /* PCI-E */
pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(7, 0)); // PCI-E
+ dev = dev_find_slot(0, PCI_DEVFN(7, 0)); /* PCI-E */
pci_write_config8(dev, 0x3C, 0x0A);
- dev = dev_find_slot(0, PCI_DEVFN(15, 0)); // Azalia
+ dev = dev_find_slot(0, PCI_DEVFN(15, 0)); /* Azalia */
pci_write_config8(dev, 0x3C, 0x05);
}
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
index 1544205..6783bbd 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
@@ -24,7 +24,7 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_sis966[8]; //1
+extern unsigned char bus_sis966[8]; /* 1 */
extern unsigned apicid_sis966;
@@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
{
device_t dev;
struct resource *res;
@@ -80,13 +80,13 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sis966[bus], (((dev)<<2)|(fn)), apicid_sis966, (pin))
PCI_INT(0, sbdn+1, 1, 0xa);
- PCI_INT(0, sbdn+2, 0, 0x16); // 22
- PCI_INT(0, sbdn+2, 1, 0x17); // 23
- PCI_INT(0, sbdn+6, 1, 0x17); // 23
- PCI_INT(0, sbdn+5, 0, 0x14); // 20
- PCI_INT(0, sbdn+5, 1, 0x17); // 23
- PCI_INT(0, sbdn+5, 2, 0x15); // 21
- PCI_INT(0, sbdn+8, 0, 0x16); // 22
+ PCI_INT(0, sbdn+2, 0, 0x16); /* 22 */
+ PCI_INT(0, sbdn+2, 1, 0x17); /* 23 */
+ PCI_INT(0, sbdn+6, 1, 0x17); /* 23 */
+ PCI_INT(0, sbdn+5, 0, 0x14); /* 20 */
+ PCI_INT(0, sbdn+5, 1, 0x17); /* 23 */
+ PCI_INT(0, sbdn+5, 2, 0x15); /* 21 */
+ PCI_INT(0, sbdn+8, 0, 0x16); /* 22 */
for(j = 7; j >= 2; j--) {
if(!bus_sis966[j]) continue;
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
index 35c54c8..3ca111b 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c
@@ -132,7 +132,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -167,7 +166,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -194,7 +192,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -224,7 +221,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -265,7 +261,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
+ /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 337423f..d542bf5 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -100,10 +100,10 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // Node 1
+ /* Node 1 */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
@@ -136,12 +136,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
+ set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
+ setup_coherent_ht_domain(); /* routing table and start other core0 */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
+ /* It is said that we should start core1 after all core0 launched */
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
@@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
/* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+ ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
#if CONFIG_SET_FIDVID
{
@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
+ /* show final fid and vid */
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -173,25 +173,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
+ /* fidvid change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now;
+ /* It's the time to set ctrl in sysinfo now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
sis_init_stage1();
enable_smbus();
- //do we need apci timer, tsc...., only debug need it for better output
+ /* do we need apci timer, tsc...., only debug need it for better output */
/* all ap stopped? */
-// init_timer(); // Need to use TMICT to synchronize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
sis_init_stage2();
- post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
+ post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */
}
diff --git a/src/mainboard/gigabyte/m57sli/fanctl.c b/src/mainboard/gigabyte/m57sli/fanctl.c
index cc0cdca..dca02d2 100644
--- a/src/mainboard/gigabyte/m57sli/fanctl.c
+++ b/src/mainboard/gigabyte/m57sli/fanctl.c
@@ -32,8 +32,6 @@ static const struct {
{ 0x51, 0x1c},
/* set the 'zero' voltage for diode type sensor 3 */
{ 0x5c, 0x80},
-// { 0x56, 0xe5},
-// { 0x57, 0xe5},
{ 0x59, 0xec},
{ 0x5c, 0x00},
/* fan1 (controlled by temp3) control parameters */
@@ -41,8 +39,6 @@ static const struct {
{ 0x60, 0xff},
/* fan start limit */
{ 0x61, 0x14},
- /* ???? */
-// { 0x62, 0x00},
/* start PWM */
{ 0x63, 0x27},
/* smooth and slope PWM */
diff --git a/src/mainboard/gigabyte/m57sli/get_bus_conf.c b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
index 9d13b0c..2b32bc4 100644
--- a/src/mainboard/gigabyte/m57sli/get_bus_conf.c
+++ b/src/mainboard/gigabyte/m57sli/get_bus_conf.c
@@ -25,32 +25,18 @@
#include <cpu/amd/amdk8_sysconf.h>
#include <stdlib.h>
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-//busnum is default
-unsigned char bus_mcp55[8]; //1
+/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
+/* busnum is default */
+unsigned char bus_mcp55[8]; /* 1 */
unsigned apicid_mcp55;
-unsigned pci1234x[] = { //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+unsigned pci1234x[] = { /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */
+ /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
};
-unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+unsigned hcdnx[] = { /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
};
static unsigned get_bus_conf_done = 0;
@@ -65,7 +51,7 @@ void get_bus_conf(void)
int i;
if (get_bus_conf_done == 1)
- return; //do it only once
+ return; /* do it only once */
get_bus_conf_done = 1;
@@ -77,7 +63,7 @@ void get_bus_conf(void)
get_sblk_pci1234();
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */
sbdn = sysconf.sbdn;
for (i = 0; i < 8; i++) {
@@ -110,7 +96,7 @@ void get_bus_conf(void)
}
}
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
apicid_base = get_apicid_base(1);
else
diff --git a/src/mainboard/gigabyte/m57sli/irq_tables.c b/src/mainboard/gigabyte/m57sli/irq_tables.c
index 4d42d74..cd8663e 100644
--- a/src/mainboard/gigabyte/m57sli/irq_tables.c
+++ b/src/mainboard/gigabyte/m57sli/irq_tables.c
@@ -43,7 +43,7 @@ static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus,
pirq_info->rfu = rfu;
}
-extern unsigned char bus_mcp55[8]; //1
+extern unsigned char bus_mcp55[8]; /* 1 */
unsigned long write_pirq_routing_table(unsigned long addr)
{
@@ -57,7 +57,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t sum = 0;
int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
sbdn = sysconf.sbdn;
/* Align the table to be 16 byte aligned. */
@@ -87,7 +87,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
-//pci bridge
+/* pci bridge */
write_pirq_info(pirq_info, bus_mcp55[0], ((sbdn + 6) << 3) | 0, 0x1,
0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
pirq_info++;
diff --git a/src/mainboard/gigabyte/m57sli/mptable.c b/src/mainboard/gigabyte/m57sli/mptable.c
index 019a7f5..66021ea 100644
--- a/src/mainboard/gigabyte/m57sli/mptable.c
+++ b/src/mainboard/gigabyte/m57sli/mptable.c
@@ -23,7 +23,7 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_mcp55[8]; //1
+extern unsigned char bus_mcp55[8]; /* 1 */
extern unsigned apicid_mcp55;
diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c
index 35c54c8..3ca111b 100644
--- a/src/mainboard/gigabyte/m57sli/resourcemap.c
+++ b/src/mainboard/gigabyte/m57sli/resourcemap.c
@@ -132,7 +132,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -167,7 +166,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -194,7 +192,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -224,7 +221,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -265,7 +261,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
+ /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index b12b12c..81659fa 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -91,10 +91,10 @@ static void sio_setup(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // Node 1
+ /* Node 1 */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
@@ -113,23 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
-#if 0
- uint8_t tmp = 0;
- pnp_enter_ext_func_mode(SERIAL_DEV);
- /* The following line will set CLKIN to 24 MHz, external */
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11);
- tmp = pnp_read_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP);
- /* Is serial flash enabled? Then enable writing to serial flash. */
- if (tmp & 0x0e) {
- pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_SWSUSP, tmp | 0x10);
- pnp_set_logical_device(GPIO_DEV);
- /* Set Serial Flash interface to 0x0820 */
- pnp_write_config(GPIO_DEV, 0x64, 0x08);
- pnp_write_config(GPIO_DEV, 0x65, 0x20);
- }
- it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
- pnp_exit_ext_func_mode(SERIAL_DEV);
-#endif
ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48);
ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -143,12 +126,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
- setup_coherent_ht_domain(); // routing table and start other core0
+ set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
+ setup_coherent_ht_domain(); /* routing table and start other core0 */
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
+ /* It is said that we should start core1 after all core0 launched */
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
@@ -158,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
/* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+ ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
#if CONFIG_SET_FIDVID
{
@@ -169,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
+ /* show final fid and vid */
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -177,20 +160,20 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
#endif
- init_timer(); // Need to use TMICT to synchronize FID/VID
+ init_timer(); /* Need to use TMICT to synchronize FID/VID */
needs_reset |= optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
+ /* fidvid change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now;
+ /* It's the time to set ctrl in sysinfo now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
@@ -199,5 +182,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now
+ post_cache_as_ram(); /* bsp swtich stack to RAM and copy sysinfo RAM now */
}
diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c
index ac53c43..82bdf63 100644
--- a/src/mainboard/gigabyte/ma785gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gm/mainboard.c
@@ -92,7 +92,7 @@ int is_dev3_present(void)
static void set_gpio40_gfx(void)
{
u8 byte;
-// u16 word;
+/* u16 word; */
u32 dword;
device_t sm_dev;
/* disable the GPIO40 as CLKREQ2# function */
@@ -135,7 +135,6 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "Mainboard MA785GM-US2H Enable. dev=0x%p\n", dev);
set_pcie_dereset();
- /* get_ide_dma66(); */
set_gpio40_gfx();
}
diff --git a/src/mainboard/gigabyte/ma785gm/resourcemap.c b/src/mainboard/gigabyte/ma785gm/resourcemap.c
index 95d009a..d696c4d 100644
--- a/src/mainboard/gigabyte/ma785gm/resourcemap.c
+++ b/src/mainboard/gigabyte/ma785gm/resourcemap.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-
-
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
@@ -45,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -83,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ /* don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -131,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -166,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -193,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -223,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -264,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 06eaa8c..ca2f4c7 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -13,9 +13,7 @@
* GNU General Public License for more details.
*/
-//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
#include <stdint.h>
#include <string.h>
@@ -99,12 +97,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_disable_reboot(GPIO_DEV);
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -163,10 +159,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -193,8 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-// die("Die Before MCT init.");
-
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@@ -205,21 +199,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// die("After MCT init before CAR disabled.");
-
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c
index 187c30e..43cbe52 100644
--- a/src/mainboard/gigabyte/ma785gmt/mainboard.c
+++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c
@@ -122,7 +122,7 @@ int is_dev3_present(void)
static void set_gpio40_gfx(void)
{
u8 byte;
-// u16 word;
+/* u16 word; */
u32 dword;
device_t sm_dev;
/* disable the GPIO40 as CLKREQ2# function */
@@ -143,8 +143,8 @@ static void set_gpio40_gfx(void)
/* access the smbus extended register */
sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
- /*if the dev3 is present, set the gfx to 2x8 lanes*/
- /*otherwise set the gfx to 1x16 lanes*/
+ /* if the dev3 is present, set the gfx to 2x8 lanes*/
+ /* otherwise set the gfx to 1x16 lanes*/
if(is_dev3_present()){
printk(BIOS_INFO, "Dev3 is present. GFX Configuration is Two x8 slots\n");
@@ -221,19 +221,6 @@ static void set_thermal_config(void)
byte &= 0xf3;
pm_iowrite(0x3c, byte);
- /* THERMTRIP pin */
- /* byte = pm_ioread(0x68);
- * byte |= 1 << 3;
- * pm_iowrite(0x68, byte);
- *
- * byte = pm_ioread(0x55);
- * byte |= 1 << 0;
- * pm_iowrite(0x55, byte);
- *
- * byte = pm_ioread(0x67);
- * byte &= ~( 1 << 6);
- * pm_iowrite(0x67, byte);
- */
}
/*************************************************
@@ -245,7 +232,6 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "Mainboard MA785GMT-UD2H Enable. dev=0x%p\n", dev);
set_pcie_dereset();
- /* get_ide_dma66(); */
set_thermal_config();
set_gpio40_gfx();
}
diff --git a/src/mainboard/gigabyte/ma785gmt/resourcemap.c b/src/mainboard/gigabyte/ma785gmt/resourcemap.c
index 95d009a..d696c4d 100644
--- a/src/mainboard/gigabyte/ma785gmt/resourcemap.c
+++ b/src/mainboard/gigabyte/ma785gmt/resourcemap.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-
-
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
@@ -45,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -83,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ /* don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -131,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -166,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -193,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -223,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -264,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 860b1f1..2496148 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -13,9 +13,7 @@
* GNU General Public License for more details.
*/
-//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
#include <stdint.h>
#include <string.h>
@@ -99,12 +97,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
it8718f_disable_reboot(GPIO_DEV);
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -163,10 +159,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -193,8 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-// die("Die Before MCT init.");
-
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@@ -205,21 +199,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// die("After MCT init before CAR disabled.");
-
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c
index 505ba3e..c0dda77 100644
--- a/src/mainboard/gigabyte/ma78gm/mainboard.c
+++ b/src/mainboard/gigabyte/ma78gm/mainboard.c
@@ -72,7 +72,6 @@ static void mainboard_enable(device_t dev)
printk(BIOS_INFO, "Mainboard MA78GM-US2H Enable. dev=0x%p\n", dev);
set_pcie_dereset();
- /* get_ide_dma66(); */
}
struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/gigabyte/ma78gm/resourcemap.c b/src/mainboard/gigabyte/ma78gm/resourcemap.c
index 95d009a..d696c4d 100644
--- a/src/mainboard/gigabyte/ma78gm/resourcemap.c
+++ b/src/mainboard/gigabyte/ma78gm/resourcemap.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-
-
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
@@ -45,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -83,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ /* don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -131,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -166,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -193,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -223,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -264,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index 9efda6f..039470e 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -13,11 +13,9 @@
* GNU General Public License for more details.
*/
-//#define SYSTEM_TYPE 0 /* SERVER */
#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
-//used by incoherent_ht
+/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@@ -107,7 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -166,10 +164,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -196,8 +194,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-// die("Die Before MCT init.");
-
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@@ -208,21 +204,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// die("After MCT init before CAR disabled.");
-
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
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