[coreboot-gerrit] Patch set updated for coreboot: mainboard/hp: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Oct 7 12:58:45 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16915
-gerrit
commit 1e873cd83599e82698515fb4da256eab25db0f5f
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Oct 7 12:51:08 2016 +0200
mainboard/hp: Use C89 comments style & remove commented code
Change-Id: I6a38b923a1a2e701cae31d3a6eeacb0eec3e581e
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/hp/abm/BiosCallOuts.c | 2 +-
src/mainboard/hp/abm/OptionsIds.h | 10 --
src/mainboard/hp/abm/buildOpts.c | 147 +++++----------------
src/mainboard/hp/abm/mptable.c | 4 -
src/mainboard/hp/abm/romstage.c | 6 +-
src/mainboard/hp/dl145_g1/acpi_tables.c | 47 -------
src/mainboard/hp/dl145_g1/fadt.c | 49 ++-----
src/mainboard/hp/dl145_g1/get_bus_conf.c | 26 +---
src/mainboard/hp/dl145_g1/irq_tables.c | 8 +-
src/mainboard/hp/dl145_g1/mptable.c | 32 ++---
src/mainboard/hp/dl145_g1/resourcemap.c | 2 -
src/mainboard/hp/dl145_g1/romstage.c | 19 +--
src/mainboard/hp/dl145_g3/get_bus_conf.c | 27 ++--
src/mainboard/hp/dl145_g3/irq_tables.c | 35 +++--
src/mainboard/hp/dl145_g3/mptable.c | 37 ++----
src/mainboard/hp/dl145_g3/romstage.c | 45 ++-----
src/mainboard/hp/dl165_g6_fam10/bootblock.c | 1 -
src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c | 8 +-
src/mainboard/hp/dl165_g6_fam10/mptable.c | 14 +-
src/mainboard/hp/dl165_g6_fam10/romstage.c | 15 +--
src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 10 +-
src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h | 10 --
src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 139 ++++++-------------
src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 -
24 files changed, 187 insertions(+), 507 deletions(-)
diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c
index 70573be..c0487b5 100644
--- a/src/mainboard/hp/abm/BiosCallOuts.c
+++ b/src/mainboard/hp/abm/BiosCallOuts.c
@@ -52,7 +52,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ /* logical devicd 3 */
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE;
} else if (StdHeader->Func == AMD_INIT_ENV) {
diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h
index 544ac53..f8977f5 100644
--- a/src/mainboard/hp/abm/OptionsIds.h
+++ b/src/mainboard/hp/abm/OptionsIds.h
@@ -48,17 +48,7 @@
**/
#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
-//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
#endif /* _OPTION_IDS_H_ */
diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c
index 2f31c5e..e90bca0 100644
--- a/src/mainboard/hp/abm/buildOpts.c
+++ b/src/mainboard/hp/abm/buildOpts.c
@@ -58,36 +58,22 @@
#endif
#endif
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
-#define BLDOPT_REMOVE_SRAT FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_CDIT TRUE
#define BLDOPT_REMOVE_DMI TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+/* This element selects whether P-States should be forced to be independent,
+ * as reported by the ACPI _PSD object. For single-link processors,
+ * setting TRUE for OS to support this feature.
+ */
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -109,11 +95,11 @@
#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
#define BLDCFG_MEM_INIT_PSTATE 0
-#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
- // core for C-state entry requests. A value
- // of 0 in this field specifies that the core
- // does not trap any IO addresses for C-state entry.
- // Values greater than 0xFFF8 results in undefined behavior.
+#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 /* Specifies the IO addresses trapped by the */
+ /* core for C-state entry requests. A value */
+ /* of 0 in this field specifies that the core */
+ /* does not trap any IO addresses for C-state entry. */
+ /* Values greater than 0xFFF8 results in undefined behavior. */
#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
@@ -154,15 +140,10 @@
#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
#define BLDCFG_IOMMU_SUPPORT FALSE
#define OPTION_GFX_INIT_SVIEW FALSE
-//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
-//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
#define BLDCFG_CFG_ABM_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
#ifdef PCIEX_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
@@ -179,43 +160,6 @@
/*
* Customized OEM build configurations for FCH component
*/
-// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
-// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
-// #define BLDCFG_AZALIA_SSID 0x780D1022
-// #define BLDCFG_SMBUS_SSID 0x780B1022
-// #define BLDCFG_IDE_SSID 0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID 0x78011022
-// #define BLDCFG_SATA_IDE_SSID 0x78001022
-// #define BLDCFG_SATA_RAID5_SSID 0x78031022
-// #define BLDCFG_SATA_RAID_SSID 0x78021022
-// #define BLDCFG_EHCI_SSID 0x78081022
-// #define BLDCFG_OHCI_SSID 0x78071022
-// #define BLDCFG_LPC_SSID 0x780E1022
-// #define BLDCFG_SD_SSID 0x78061022
-// #define BLDCFG_XHCI_SSID 0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
{
@@ -249,40 +193,21 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#include "cpuLateInit.h"
#include "GnbInterface.h"
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-//#define DDR400_FREQUENCY 200 ///< DDR 400
-//#define DDR533_FREQUENCY 266 ///< DDR 533
-//#define DDR667_FREQUENCY 333 ///< DDR 667
-//#define DDR800_FREQUENCY 400 ///< DDR 800
-//#define DDR1066_FREQUENCY 533 ///< DDR 1066
-//#define DDR1333_FREQUENCY 667 ///< DDR 1333
-//#define DDR1600_FREQUENCY 800 ///< DDR 1600
-//#define DDR1866_FREQUENCY 933 ///< DDR 1866
-//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
-//
-///* QUANDRANK_TYPE*/
-//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
-//
-///* USER_MEMORY_TIMING_MODE */
-//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
-//
-///* POWER_DOWN_MODE */
-//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+
+/* QUANDRANK_TYPE*/
+
+/* USER_MEMORY_TIMING_MODE */
+
+/* POWER_DOWN_MODE */
/*
* Agesa optional capabilities selection.
@@ -327,26 +252,26 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-//#define BLDCFG_IR_PIN_CONTROL 0x33
GPIO_CONTROL hp_abm_gpio[] = {
- { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED
- { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID
- { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH
- { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT
- { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L
- { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC
- { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L
- { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT
- { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT
- { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R
+ { 45, Function2, GpioOutEnB | Sticky }, /* Signal input APU_SD_LED */
+ { 49, Function2, PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_UID */
+ { 50, Function2, PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_HEALTH */
+ { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, /* Signal output APU_ABM_LED_FAULT */
+ { 57, Function2, GpioOutEnB | Sticky }, /* Signal input SATA_PRSNT_L */
+ { 58, Function2, GpioOutEnB | Sticky }, /* Signal i/o APU_HDMI_CEC */
+ { 64, Function2, GpioOutEnB | Sticky }, /* Signal input SWC_APU_INT_L */
+ { 68, Function0, GpioOutEnB | Sticky }, /* Signal input CNTRL1_PRSNT */
+ { 69, Function0, GpioOutEnB | Sticky }, /* Signal input CNTRL2_PRSNT */
+ { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, /* Signal output APU_PROCHOT_L_R */
{-1}
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c
index 6241282..4ff8ea1 100644
--- a/src/mainboard/hp/abm/mptable.c
+++ b/src/mainboard/hp/abm/mptable.c
@@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
@@ -113,9 +112,6 @@ static void *smp_write_config_table(void *v)
outb(0x48, 0xCD6);
outb(0xF2, 0xCD7);
- //outb(0xBE, 0xCD6);
- //outb(0x52, 0xCD7);
-
outb(0xED, 0xCD6);
outb(0x17, 0xCD7);
diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c
index 6e77c57..4d3daed 100644
--- a/src/mainboard/hp/abm/romstage.c
+++ b/src/mainboard/hp/abm/romstage.c
@@ -60,14 +60,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */
addr32 = (u32 *)0xfed80e28;
t32 = *addr32;
- t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16]
- t32 |= 0x00010000; // Set bit 16 for 25MHz
+ t32 &= 0xffc0ffff; /* Clr bits [21:19] & [18:16] */
+ t32 |= 0x00010000; /* Set bit 16 for 25MHz */
*addr32 = t32;
/* Enable Auxiliary OSCOUT1/OSCOUT2 */
addr32 = (u32 *)0xfed80e40;
t32 = *addr32;
- t32 &= 0xffffff7b; // clear 2, 7
+ t32 &= 0xffffff7b; /* clear 2, 7 */
*addr32 = t32;
if (!cpu_init_detectedx && boot_cpu()) {
diff --git a/src/mainboard/hp/dl145_g1/acpi_tables.c b/src/mainboard/hp/dl145_g1/acpi_tables.c
index 47e0a3a..d5dd1dc 100644
--- a/src/mainboard/hp/dl145_g1/acpi_tables.c
+++ b/src/mainboard/hp/dl145_g1/acpi_tables.c
@@ -63,53 +63,6 @@ unsigned long acpi_fill_madt(unsigned long current)
gsi_base+=4;
}
}
-
- /*
- int i;
- int j = 0;
-
- for(i = 1; i< sysconf.hc_possible_num; i++) {
- unsigned d = 0;
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
- // 8131 need to use +4
-
- switch (sysconf.hcid[i]) {
- case 1:
- d = 7;
- break;
- case 3:
- d = 4;
- break;
- }
- switch (sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
- res->base, gsi_base );
- gsi_base+=d;
- }
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
- res->base, gsi_base );
- gsi_base+=d;
-
- }
- }
- break;
- }
-
- j++;
- }
- */
-
}
current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
diff --git a/src/mainboard/hp/dl145_g1/fadt.c b/src/mainboard/hp/dl145_g1/fadt.c
index 877cb5b..fd7a807 100644
--- a/src/mainboard/hp/dl145_g1/fadt.c
+++ b/src/mainboard/hp/dl145_g1/fadt.c
@@ -28,12 +28,12 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->firmware_ctrl=(u32)facs;
fadt->dsdt= (u32)dsdt;
- // 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server
+ /* 3 = Workstation, 4 = Enterprise Server, 7 = Performance Server */
fadt->preferred_pm_profile = 0x04;
fadt->sci_int = 9;
- // disable system management mode by setting to 0:
- fadt->smi_cmd = 0;//pm_base+0x2f;
+ /* disable system management mode by setting to 0: */
+ fadt->smi_cmd = 0;/* pm_base+0x2f; */
fadt->acpi_enable = 0xf0;
fadt->acpi_disable = 0xf1;
fadt->s4bios_req = 0x0;
@@ -57,47 +57,27 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->gpe1_base = 16;
fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101; // > 100 means system doesnt support C2 state
- fadt->p_lvl3_lat = 1001; // > 1000 means system doesnt support C3 state
- fadt->flush_size = 0; // ignored if wbindv = 1 in flags
- fadt->flush_stride = 0; // ignored if wbindv = 1 in flags
+ fadt->p_lvl2_lat = 101; /* 100 means system doesnt support C2 state */
+ fadt->p_lvl3_lat = 1001; /* 1000 means system doesnt support C3 state */
+ fadt->flush_size = 0; /* ignored if wbindv = 1 in flags */
+ fadt->flush_stride = 0; /* ignored if wbindv = 1 in flags */
fadt->duty_offset = 1;
- fadt->duty_width = 3; // 0 means duty cycle not supported
- // _alrm value 0 means RTC alarm feature not supported
- fadt->day_alrm = 0; // 0x7d these have to be
- fadt->mon_alrm = 0; // 0x7e added to cmos.layout
- fadt->century = 0; // 0x7f to make rtc alrm work
+ fadt->duty_width = 3; /* 0 means duty cycle not supported */
+ /* _alrm value 0 means RTC alarm feature not supported */
+ fadt->day_alrm = 0; /* 0x7d these have to be */
+ fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */
+ fadt->century = 0; /* 0x7f to make rtc alrm work */
fadt->iapc_boot_arch =
ACPI_FADT_LEGACY_DEVICES |
ACPI_FADT_8042 |
- // ACPI_FADT_VGA_NOT_PRESENT |
- // ACPI_FADT_MSI_NOT_SUPPORTED|
- // ACPI_FADT_NO_PCIE_ASPM_CONTROL|
0;
fadt->res2 = 0;
fadt->flags =
ACPI_FADT_WBINVD |
- // ACPI_FADT_WBINVD_FLUSH |
ACPI_FADT_C1_SUPPORTED |
- // ACPI_FADT_C2_MP_SUPPORTED |
- // ACPI_FADT_POWER_BUTTON |
ACPI_FADT_SLEEP_BUTTON |
- // ACPI_FADT_FIXED_RTC |
- // ACPI_FADT_S4_RTC_WAKE |
- // ACPI_FADT_32BIT_TIMER |
- // ACPI_FADT_DOCKING_SUPPORTED|
- // ACPI_FADT_RESET_REGISTER |
- // ACPI_FADT_SEALED_CASE |
- // ACPI_FADT_HEADLESS |
- // ACPI_FADT_SLEEP_TYPE |
- // ACPI_FADT_PCI_EXPRESS_WAKE |
- // ACPI_FADT_PLATFORM_CLOCK |
- // ACPI_FADT_S4_RTC_VALID |
- // ACPI_FADT_REMOTE_POWER_ON |
- // ACPI_FADT_APIC_CLUSTER |
- // ACPI_FADT_APIC_PHYSICAL |
0;
fadt->reset_reg.space_id = 1;
@@ -146,7 +126,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm1b_cnt_blk.addrl = 0x0;
fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
fadt->x_pm2_cnt_blk.space_id = 1;
fadt->x_pm2_cnt_blk.bit_width = 0;
fadt->x_pm2_cnt_blk.bit_offset = 0;
@@ -154,7 +133,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm2_cnt_blk.addrl = 0x0;
fadt->x_pm2_cnt_blk.addrh = 0x0;
-
fadt->x_pm_tmr_blk.space_id = 1;
fadt->x_pm_tmr_blk.bit_width = 32;
fadt->x_pm_tmr_blk.bit_offset = 0;
@@ -162,7 +140,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
fadt->x_pm_tmr_blk.addrh = 0x0;
-
fadt->x_gpe0_blk.space_id = 1;
fadt->x_gpe0_blk.bit_width = 32;
fadt->x_gpe0_blk.bit_offset = 0;
@@ -170,7 +147,6 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_gpe0_blk.addrl = pm_base+0x20;
fadt->x_gpe0_blk.addrh = 0x0;
-
fadt->x_gpe1_blk.space_id = 1;
fadt->x_gpe1_blk.bit_width = 64;
fadt->x_gpe1_blk.bit_offset = 16;
@@ -179,5 +155,4 @@ void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
fadt->x_gpe1_blk.addrh = 0x0;
header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
}
diff --git a/src/mainboard/hp/dl145_g1/get_bus_conf.c b/src/mainboard/hp/dl145_g1/get_bus_conf.c
index da02095..a52e3ab 100644
--- a/src/mainboard/hp/dl145_g1/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g1/get_bus_conf.c
@@ -14,31 +14,17 @@
#include "mb_sysconf.h"
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
struct mb_sysconf_t mb_sysconf;
static unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+{ /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */
+ /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
};
static unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+{ /* HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
};
@@ -52,7 +38,7 @@ void get_bus_conf(void)
device_t dev;
int i;
- if(get_bus_conf_done == 1) return; //do it only once
+ if(get_bus_conf_done == 1) return; /* do it only once */
get_bus_conf_done = 1;
@@ -101,7 +87,7 @@ void get_bus_conf(void)
}
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
apicid_base = get_apicid_base(3);
else
diff --git a/src/mainboard/hp/dl145_g1/irq_tables.c b/src/mainboard/hp/dl145_g1/irq_tables.c
index 597acca..88275c8 100644
--- a/src/mainboard/hp/dl145_g1/irq_tables.c
+++ b/src/mainboard/hp/dl145_g1/irq_tables.c
@@ -38,7 +38,7 @@ unsigned long write_pirq_routing_table(unsigned long addr)
uint8_t sum = 0;
int i;
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+ get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */
/* Align the table to be 16 byte aligned. */
addr += 15;
@@ -67,15 +67,12 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info = (void *)(&pirq->checksum + 1);
slot_num = 0;
-//pci bridge
+/* pci bridge */
write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn + 1) << 3) | 0,
0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0,
0);
pirq_info++;
slot_num++;
-//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8131_0, (m->sbdn3 << 3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-// pirq_info++; slot_num++;
pirq_info++;
slot_num++;
@@ -94,5 +91,4 @@ unsigned long write_pirq_routing_table(unsigned long addr)
printk(BIOS_INFO, "done.\n");
return (unsigned long)pirq_info;
-
}
diff --git a/src/mainboard/hp/dl145_g1/mptable.c b/src/mainboard/hp/dl145_g1/mptable.c
index 1a9132e..c4bc0db 100644
--- a/src/mainboard/hp/dl145_g1/mptable.c
+++ b/src/mainboard/hp/dl145_g1/mptable.c
@@ -28,7 +28,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x20, VIO_APIC_VADDR);
{
device_t dev;
@@ -54,31 +54,23 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
- //
- // The commented-out lines are auto-detected on my servers.
- //
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- // Integrated SMBus 2.0
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|3, apicid_8111 , 0x15);
- // Integrated AMD AC97 Audio
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|1, apicid_8111 , 0x11);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ( 0x4 <<2)|2, apicid_8111 , 0x12);
- // Integrated AMD USB
+ /* The commented-out lines are auto-detected on my servers. */
+
+/* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ /* Integrated SMBus 2.0 */
+
+ /* Integrated AMD USB */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x4 <<2)|0, m->apicid_8111 , 0x10);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x0 <<2)|3, m->apicid_8111 , 0x13);
- // On board ATI Rage XL
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, ( 0x5 <<2)|0, apicid_8111 , 0x14);
- // On board Broadcom nics
+ /* On board ATI Rage XL */
+
+ /* On board Broadcom nics */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|0, m->apicid_8131_2, 0x03);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x3 <<2)|1, m->apicid_8131_2, 0x00);
- // On board LSI SCSI
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_2, ( 0x2 <<2)|0, apicid_8131_2, 0x02);
+ /* On board LSI SCSI */
- // PCIX-133 Slot
+ /* PCIX-133 Slot */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|0, m->apicid_8131_1, 0x01);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|1, apicid_8131_1, 0x02);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|2, apicid_8131_1, 0x03);
- //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8131_1, ( 0x1 <<2)|3, apicid_8131_1, 0x04);
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
mptable_lintsrc(mc, bus_isa);
diff --git a/src/mainboard/hp/dl145_g1/resourcemap.c b/src/mainboard/hp/dl145_g1/resourcemap.c
index 65a4610..8a43841 100644
--- a/src/mainboard/hp/dl145_g1/resourcemap.c
+++ b/src/mainboard/hp/dl145_g1/resourcemap.c
@@ -120,7 +120,6 @@ static void setup_dl145g1_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- //PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000b20,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
@@ -156,7 +155,6 @@ static void setup_dl145g1_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- //PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000a03,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index ea0b60c..b295ca7 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -97,11 +97,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- //first node
+ /* first node */
RC0|DIMM0, RC0|DIMM2, 0, 0,
RC0|DIMM1, RC0|DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
+ /* second node */
RC1|DIMM0, RC1|DIMM2, 0, 0,
RC1|DIMM1, RC1|DIMM3, 0, 0,
#endif
@@ -123,12 +123,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_dl145g1_resource_map();
- //setup_default_resource_map();
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
+ /* It is said that we should start core1 after all core0 launched */
start_other_cores();
wait_all_other_cores_started(bsp_apicid);
#endif
@@ -150,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
+ /* show final fid and vid */
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -180,22 +179,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
change_i2c_mux(i);
}
- //dump_spd_registers(&sysinfo->ctrl[0]);
- //dump_spd_registers(&sysinfo->ctrl[1]);
- //dump_smbus_registers();
-
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl now;
+ /* It's the time to set ctrl now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
memreset_setup();
#if CONFIG_SET_FIDVID
- init_timer(); // Need to use TMICT to synchronize FID/VID
+ init_timer(); /* Need to use TMICT to synchronize FID/VID */
#endif
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
- //dump_pci_devices();
-
post_cache_as_ram();
}
diff --git a/src/mainboard/hp/dl145_g3/get_bus_conf.c b/src/mainboard/hp/dl145_g3/get_bus_conf.c
index d69e224..12f7b89 100644
--- a/src/mainboard/hp/dl145_g3/get_bus_conf.c
+++ b/src/mainboard/hp/dl145_g3/get_bus_conf.c
@@ -17,6 +17,7 @@
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
+
#include <console/console.h>
#include <device/pci.h>
#include <device/pci_ids.h>
@@ -28,31 +29,19 @@
#include "mb_sysconf.h"
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
struct mb_sysconf_t mb_sysconf;
static unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+{ /* Here you only need to set value in pci1234 for HT-IO that could be installed or not */
+ /* You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail */
0x0000ff0,
0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
};
static unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+{ /*HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most */
0x20202020,
0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
};
@@ -68,7 +57,7 @@ void get_bus_conf(void)
int i;
struct mb_sysconf_t *m;
- if(get_bus_conf_done == 1) return; //do it only once
+ if(get_bus_conf_done == 1) return; /* do it only once */
get_bus_conf_done = 1;
@@ -86,7 +75,7 @@ void get_bus_conf(void)
get_sblk_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
+ m->sbdn2 = sysconf.hcdn[0] & 0xff; /* bcm5780 */
m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 16) & 0xff;
m->bus_bcm5780[0] = m->bus_bcm5785_0;
@@ -120,7 +109,7 @@ void get_bus_conf(void)
}
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
if (IS_ENABLED(CONFIG_LOGICAL_CPUS))
apicid_base = get_apicid_base(3);
else
diff --git a/src/mainboard/hp/dl145_g3/irq_tables.c b/src/mainboard/hp/dl145_g3/irq_tables.c
index 6ec1fd8..f2937b1 100644
--- a/src/mainboard/hp/dl145_g3/irq_tables.c
+++ b/src/mainboard/hp/dl145_g3/irq_tables.c
@@ -20,26 +20,21 @@ static const struct irq_routing_table intel_irq_routing_table = {
bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 legacy southbridge
- {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 usb
- {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // VGA Contr
- {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom ht1000 pci/pci-x bridge
- {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom BCM5785 [HT1000] SATA
- {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5785 [HT1000] PCI/PCI-X Bridge
- //{0x02,(0x01 << 3)|0x0, {{0x11, 0x08a8}, {0x12, 0x08a8}, {0x13, 0x08a8}, {0x14, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x03,(0x00 << 3)|0x0, {{0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x08a8}, {0x21, 0x008a8}}, 0x1, 0x0},
- {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x06,(0x00 << 3)|0x0, {{0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x08a8}, {0x24, 0x008a8}}, 0x2, 0x0},
- {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Broadcom HT2100 PCI-Express Bridge
- //{0x07,(0x00 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0},
- {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // BCM5715 Gigabit Ethernet
- {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // Host Bridge
- //{0x10,(0x01 << 3)|0x0, {{0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x8000}, {0x28, 0x08000}}, 0x1, 0x0},
- {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, // HTX slot
+ {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Host Bridge */
+ {0x00,(0x02 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 legacy southbridge */
+ {0x00,(0x03 << 3)|0x0, {{0x02, 0x0400}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 usb */
+ {0x00,(0x04 << 3)|0x0, {{0x18, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* VGA Contr */
+ {0x00,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom ht1000 pci/pci-x bridge */
+ {0x01,(0x0e << 3)|0x0, {{0x08, 0x00a0}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom BCM5785 [HT1000] SATA */
+ {0x01,(0x0d << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* BCM5785 [HT1000] PCI/PCI-X Bridge */
+ {0x00,(0x06 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */
+ {0x00,(0x07 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */
+ {0x00,(0x08 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */
+ {0x00,(0x09 << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */
+ {0x00,(0x0a << 3)|0x0, {{0x2f, 0x08a8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Broadcom HT2100 PCI-Express Bridge */
+ {0x08,(0x04 << 3)|0x0, {{0x25, 0x08a8}, {0x25, 0x08a8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* BCM5715 Gigabit Ethernet */
+ {0x00,(0x18 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* Host Bridge */
+ {0x40,(0x01 << 3)|0x0, {{0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0xdef8}, {0x00, 0x0def8}}, 0x0, 0x0}, /* HTX slot */
}
};
diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c
index 3a784e7..c7ab385 100644
--- a/src/mainboard/hp/dl145_g3/mptable.c
+++ b/src/mainboard/hp/dl145_g3/mptable.c
@@ -52,7 +52,7 @@ static void *smp_write_config_table(void *v)
mptable_write_buses(mc, NULL, &bus_isa);
- /*I/O APICs: APIC ID Version State Address*/
+ /* I/O APICs: APIC ID Version State Address*/
{
device_t dev = 0;
int i;
@@ -74,15 +74,12 @@ static void *smp_write_config_table(void *v)
/* IRQ routing as factory BIOS */
outb(0x01, 0xc00); outb(0x0A, 0xc01);
outb(0x17, 0xc00); outb(0x05, 0xc01);
-/* outb(0x2E, 0xc00); outb(0x0B, 0xc01); */
-/* outb(0x07, 0xc00); outb(0x07, 0xc01); */
outb(0x07, 0xc00); outb(0x0b, 0xc01);
outb(0x24, 0xc00); outb(0x05, 0xc01);
- //outb(0x00, 0xc00); outb(0x09, 0xc01);
outb(0x02, 0xc00); outb(0x0E, 0xc01);
- // 8259 registers...
+ /* 8259 registers... */
outb(0xa0, 0x4d0);
outb(0x0e, 0x4d1);
@@ -92,16 +89,16 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
+ dword |= (1 << 30); /* GEVENT14-21 used as PCI IRQ0-7 */
pci_write_config32(dev, 0x64, dword);
}
- // set GEVENT pins to NO OP
+ /* set GEVENT pins to NO OP */
outb(0x33, 0xcd6); outb(0x00, 0xcd7);
outb(0x34, 0xcd6); outb(0x00, 0xcd7);
outb(0x35, 0xcd6); outb(0x00, 0xcd7);
}
- // hide XIOAPIC PCI configuration space
+ /* hide XIOAPIC PCI configuration space */
{
device_t dev;
dev = dev_find_device(0x1166, 0x205, 0);
@@ -115,31 +112,26 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
- //SATA
-/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
-/* smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0x7); */
+ /* SATA */
printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e << 2)|0, m->apicid_bcm5785[0], 0xb);
- //USB
+ /* USB */
printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03 << 2)|0, m->apicid_bcm5785[0], 0xa);
- //VGA
+ /* VGA */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x4 << 2)|0, m->apicid_bcm5785[1], 0x7);
- //PCIE
+ /* PCIE */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x6 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x7 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x8 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x9 << 2)|0, m->apicid_bcm5785[2], 0xe);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0xa << 2)|0, m->apicid_bcm5785[2], 0xe);
- //IDE
-// outb(0x02, 0xc00); outb(0x0e, 0xc01);
-// printk(BIOS_DEBUG, "MPTABLE_IDE: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_0, ((1+sysconf.sbdn)<<2)|1, m->apicid_bcm5785[0], 0xe);
-// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_bcm5785_0, (0x02 << 2)|1, m->apicid_bcm5785[0], 0xe);
+ /* IDE */
- //onboard Broadcom GbE
+ /* onboard Broadcom GbE */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|0, m->apicid_bcm5785[2], 0x4);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,8, (4 << 2)|1, m->apicid_bcm5785[2], 0x4);
@@ -153,17 +145,17 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
- dword |= (1 << 4); // enable interrupts
+ dword |= (1 << 4); /* enable interrupts */
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
}
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+/* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa);
mptable_lintsrc(mc, bus_isa);
- //extended table entries
+ /* extended table entries */
smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
@@ -174,7 +166,6 @@ static void *smp_write_config_table(void *v)
smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 0);
smp_write_compatibility_address_space(mc, 0, ADDRESS_RANGE_ADD, 1);
-
/* Compute the checksums */
return mptable_finalize(mc);
}
diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c
index 1d1195a..af9793e 100644
--- a/src/mainboard/hp/dl145_g3/romstage.c
+++ b/src/mainboard/hp/dl145_g3/romstage.c
@@ -85,28 +85,9 @@ static void setup_early_ipmi_serial()
char serial_mux2[]={0x0c << 2,0x12,0x04,0x03};
char serial_mux3[]={0x0c << 2,0x12,0x04,0x07};
-// earlydbg(0x0d);
- //set channel access system only
- ipmi_request(5,channel_access);
-// earlydbg(result);
-/*
- //Set serial/modem config
- result = ipmi_request(6,serialmodem_conf);
- earlydbg(result);
-
- //Set serial mux 1
- result = ipmi_request(4,serial_mux1);
- earlydbg(result);
- //Set serial mux 2
- result = ipmi_request(4,serial_mux2);
- earlydbg(result);
-
- //Set serial mux 3
- result = ipmi_request(4,serial_mux3);
- earlydbg(result);
-*/
-// earlydbg(0x0e);
+ /* set channel access system only */
+ ipmi_request(5,channel_access);
}
#endif
@@ -114,10 +95,10 @@ static void setup_early_ipmi_serial()
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
+ /* first node */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // second node
+ /* second node */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
@@ -144,17 +125,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-// setup_early_ipmi_serial();
- pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
+ pilot_early_init(SERIAL_DEV); /* config port is being taken from SERIAL_DEV */
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+ set_sysinfo_in_ram(0); /* in BSP so could hold all ap until sysinfo is in ram */
setup_coherent_ht_domain();
wait_all_core0_started();
#if CONFIG_LOGICAL_CPUS
- // It is said that we should start core1 after all core0 launched
+ /* It is said that we should start core1 after all core0 launched */
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
* (there may be apic id conflicts in that case)
@@ -164,7 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#endif
/* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+ ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */
bcm5785_early_setup();
#if CONFIG_SET_FIDVID
@@ -176,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
- // show final fid and vid
+ /* show final fid and vid */
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -187,7 +167,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
+ /* fidvid change will issue one LDTSTOP and the HT change will be effective too */
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@ -195,13 +175,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
allow_all_aps_stop(bsp_apicid);
- //It's the time to set ctrl in sysinfo now;
+ /*It's the time to set ctrl in sysinfo now; */
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
- //do we need apci timer, tsc...., only debug need it for better output
+ /*do we need apci timer, tsc...., only debug need it for better output */
/* all ap stopped? */
- // init_timer(); // Need to use TMICT to synchronize FID/VID
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
diff --git a/src/mainboard/hp/dl165_g6_fam10/bootblock.c b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
index 479e0b6..4286cac 100644
--- a/src/mainboard/hp/dl165_g6_fam10/bootblock.c
+++ b/src/mainboard/hp/dl165_g6_fam10/bootblock.c
@@ -28,7 +28,6 @@ void shc4307_init(void)
pnp_set_iobase(CMOS_DEV, PNP_IDX_IO0, 0x70);
pnp_set_iobase(CMOS_DEV, PNP_IDX_IO1, 0x72);
pnp_set_irq(CMOS_DEV, PNP_IDX_IRQ0, 8);
- /* pnp_set_enable(CMOS_DEV, 3); */
pnp_write_config(CMOS_DEV, 0x30, 3);
pnp_set_logical_device(KBD_DEV); /* Keyboard */
diff --git a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
index 68c3881..a20cd7b 100644
--- a/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
+++ b/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
@@ -27,7 +27,7 @@
#include <stdlib.h>
#include "mb_sysconf.h"
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+/* Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables */
struct mb_sysconf_t mb_sysconf;
/* Here you only need to set value in pci1234 for HT-IO that could be
@@ -69,7 +69,7 @@ void get_bus_conf(void)
int i;
struct mb_sysconf_t *m;
- if(get_bus_conf_done == 1) return; //do it only once
+ if(get_bus_conf_done == 1) return; /* do it only once */
get_bus_conf_done = 1;
@@ -88,7 +88,7 @@ void get_bus_conf(void)
get_pci1234();
sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn2 = sysconf.hcdn[0] & 0xff; // bcm5780
+ m->sbdn2 = sysconf.hcdn[0] & 0xff; /* bcm5780 */
m->bus_bcm5785_0 = (sysconf.pci1234[0] >> 12) & 0xff;
m->bus_bcm5780[0] = m->bus_bcm5785_0;
@@ -122,7 +122,7 @@ void get_bus_conf(void)
}
}
-/*I/O APICs: APIC ID Version State Address*/
+/* I/O APICs: APIC ID Version State Address*/
apicid_base = 0x10;
for(i = 0; i < 3; i++)
m->apicid_bcm5785[i] = apicid_base+i;
diff --git a/src/mainboard/hp/dl165_g6_fam10/mptable.c b/src/mainboard/hp/dl165_g6_fam10/mptable.c
index 17e42e4..b7aab80 100644
--- a/src/mainboard/hp/dl165_g6_fam10/mptable.c
+++ b/src/mainboard/hp/dl165_g6_fam10/mptable.c
@@ -79,7 +79,7 @@ static void *smp_write_config_table(void *v)
outb(0x03, 0xc00); outb(0x07, 0xc01);
outb(0x07, 0xc00); outb(0x05, 0xc01);
- // 8259 registers...
+ /* 8259 registers... */
outb(0xa0, 0x4d0);
outb(0x0e, 0x4d1);
@@ -89,16 +89,12 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x64);
- dword |= (1 << 30); // GEVENT14-21 used as PCI IRQ0-7
+ dword |= (1 << 30); /* GEVENT14-21 used as PCI IRQ0-7 */
pci_write_config32(dev, 0x64, dword);
}
- // set GEVENT pins to NO OP
- /* outb(0x33, 0xcd6); outb(0x00, 0xcd7);
- outb(0x34, 0xcd6); outb(0x00, 0xcd7);
- outb(0x35, 0xcd6); outb(0x00, 0xcd7); */
}
- // hide XIOAPIC PCI configuration space
+ /* hide XIOAPIC PCI configuration space */
{
device_t dev;
dev = dev_find_device(0x1166, 0x205, 0);
@@ -132,7 +128,7 @@ static void *smp_write_config_table(void *v)
if(dev) {
uint32_t dword;
dword = pci_read_config32(dev, 0x6c);
- dword |= (1 << 4); // enable interrupts
+ dword |= (1 << 4); /* enable interrupts */
printk(BIOS_DEBUG, "6ch: %x\n",dword);
pci_write_config32(dev, 0x6c, dword);
}
@@ -141,7 +137,7 @@ static void *smp_write_config_table(void *v)
/* Local Ints: Type Polarity/Trigger Bus ID IRQ APIC ID PIN# */
mptable_lintsrc(mc, isa_bus);
- //extended table entries
+ /* extended table entries */
smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
smp_write_address_space(mc,0 , ADDRESS_TYPE_MEM, 0x0, 0x7f80, 0x0, 0x5e80);
smp_write_address_space(mc,0 , ADDRESS_TYPE_PREFETCH, 0x0, 0xde00, 0x0, 0x0100);
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index 39cd0e3..5a98c23 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -78,11 +78,11 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
- // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr
- //first node
+ /* switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr */
+ /* first node */
RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
+ /* second node */
RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0,
#endif
};
@@ -118,7 +118,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
+ pilot_early_init(SERIAL_DEV); /* config port is being taken from SERIAL_DEV */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
@@ -172,10 +172,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -198,9 +198,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
enable_smbus();
- //do we need apci timer, tsc...., only debug need it for better output
+ /* do we need apci timer, tsc...., only debug need it for better output */
/* all ap stopped? */
-// init_timer(); // Need to use TMICT to synchronize FID/VID
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
index 87d6eae..231a188 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c
@@ -122,8 +122,8 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* Thermal Zone Parameter */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; //BIT0 | BIT2 | BIT5;
- FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e;//6 | BIT3;
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x3d; /*BIT0 | BIT2 | BIT5 */
+ FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x0e; /*6 | BIT3 */
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x54;
FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */
@@ -134,7 +134,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
/* IMC Fan Policy temperature thresholds */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00;
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */
- FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46;///80; /*AC0 threshold in Celsius */
+ FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0x46; /*AC0 threshold in Celsius */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0x3c; /*AC1 threshold in Celsius */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0x32; /*AC2 threshold in Celsius */
FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0xff; /*AC3 threshold in Celsius, 0xFF is not define */
@@ -157,7 +157,7 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams)
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0xff; /* AL6 percentage */
FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0xff; /* AL7 percentage */
- FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;//BIT0 | BIT4 |BIT8;
+ FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x111;/*BIT0 | BIT4 |BIT8; */
/* NOTE:
* FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege,
@@ -186,7 +186,7 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr)
if (StdHeader->Func == AMD_INIT_RESET) {
FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData;
printk(BIOS_DEBUG, "Fch OEM config in INIT RESET ");
- //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */
+ /* logical devicd 3 */
FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE);
FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE);
FchParams_reset->FchReset.Xhci1Enable = FALSE;
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h
index eaf2442..bf623f7 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h
+++ b/src/mainboard/hp/pavilion_m6_1035dx/OptionsIds.h
@@ -43,17 +43,7 @@
**/
#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
-//#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
-//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
#endif
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
index 48258ca..7763b80 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c
@@ -65,35 +65,21 @@
#define INSTALL_FM2_SOCKET_SUPPORT FALSE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
-#define BLDOPT_REMOVE_SRAT FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_DMI TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+/* This element selects whether P-States should be forced to be independent,
+ * as reported by the ACPI _PSD object. For single-link processors,
+ * setting TRUE for OS to support this feature.
+ */
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -141,7 +127,7 @@
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
#define BLDOPT_REMOVE_ALIB FALSE
@@ -153,16 +139,10 @@
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
#define BLDCFG_CFG_ABM_SUPPORT 0
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+/* Specify the default values for the VRM controlling the VDDNB plane. */
+/* If not specified, the values used for the core VRM will be applied */
+
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
@@ -172,17 +152,13 @@
#if CONFIG_GFXUMA
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* 512M */
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
@@ -190,43 +166,6 @@
/*
* Customized OEM build configurations for FCH component
*/
-// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
-// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
-// #define BLDCFG_AZALIA_SSID 0x780D1022
-// #define BLDCFG_SMBUS_SSID 0x780B1022
-// #define BLDCFG_IDE_SSID 0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID 0x78011022
-// #define BLDCFG_SATA_IDE_SSID 0x78001022
-// #define BLDCFG_SATA_RAID5_SSID 0x78031022
-// #define BLDCFG_SATA_RAID_SSID 0x78021022
-// #define BLDCFG_EHCI_SSID 0x78081022
-// #define BLDCFG_OHCI_SSID 0x78071022
-// #define BLDCFG_LPC_SSID 0x780E1022
-// #define BLDCFG_SD_SSID 0x78061022
-// #define BLDCFG_XHCI_SSID 0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
@@ -246,40 +185,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 /* DDR 400 */
+#define DDR533_FREQUENCY 266 /* DDR 533 */
+#define DDR667_FREQUENCY 333 /* DDR 667 */
+#define DDR800_FREQUENCY 400 /* DDR 800 */
+#define DDR1066_FREQUENCY 533 /* DDR 1066 */
+#define DDR1333_FREQUENCY 667 /* DDR 1333 */
+#define DDR1600_FREQUENCY 800 /* DDR 1600 */
+#define DDR1866_FREQUENCY 933 /* DDR 1866 */
+#define DDR2100_FREQUENCY 1050 /* DDR 2100 */
+#define DDR2133_FREQUENCY 1066 /* DDR 2133 */
+#define DDR2400_FREQUENCY 1200 /* DDR 2400 */
+#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 /* Use best rate possible */
+#define TIMING_MODE_LIMITED 1 /* Set user top limit */
+#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */
/*
* Agesa optional capabilities selection.
@@ -324,7 +263,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-//#define BLDCFG_IR_PIN_CONTROL 0x33
/*
* The GPIO control is not well documented in AGESA, but is in the BKDG
@@ -376,9 +314,10 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = {
};
#define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
index 9e63caf..23c0485 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c
@@ -82,7 +82,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
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