[coreboot-gerrit] Patch merged into coreboot/master: google/gru: set W2W_DIFFCS_DLY to 5

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit f08f38883ea1a5c12bd1ece1736e336c20645e7c
Author: Lin Huang <hl at rock-chips.com>
Date:   Wed Sep 21 17:05:43 2016 +0800

    google/gru: set W2W_DIFFCS_DLY to 5
    
    PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666.
    For per cs training, the controller should consider the PHY
    delay line switch time and there should be more cycles to
    switch the delay line, so update the W2W_DIFFCS_DLY_ value
    from 0x1 to 0x5.
    
    BRANCH=none
    BUG=chrome-os-partner:56940
    TEST=do memtester on kevin board, and pass
    
    Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc
    Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b
    Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/387506
    Original-Reviewed-by: Douglas Anderson <dianders at chromium.org>
    Original-Reviewed-by: Derek Basehore <dbasehore at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://review.coreboot.org/16721
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/16721 for details.

-gerrit