[coreboot-gerrit] New patch to review for coreboot: mainboard/asus: Use C89 comments style & remove commented code
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Fri Oct 7 18:05:07 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16925
-gerrit
commit 4d60f8cf8b852b897da4827915051dea8d6ceb0d
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Oct 7 17:54:44 2016 +0200
mainboard/asus: Use C89 comments style & remove commented code
Change-Id: Ic111d4d1eb9abbca04f54b95e0e2134387935889
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/mainboard/asus/a8n_e/get_bus_conf.c | 2 +-
src/mainboard/asus/a8n_e/irq_tables.c | 7 +-
src/mainboard/asus/a8n_e/mptable.c | 12 +--
src/mainboard/asus/a8n_e/romstage.c | 15 ---
src/mainboard/asus/a8v-e_deluxe/mptable.c | 28 ++---
src/mainboard/asus/a8v-e_deluxe/romstage.c | 4 +-
src/mainboard/asus/a8v-e_se/mptable.c | 28 ++---
src/mainboard/asus/a8v-e_se/romstage.c | 4 +-
src/mainboard/asus/f2a85-m/OemCustomize.c | 13 ++-
src/mainboard/asus/f2a85-m/OptionsIds.h | 10 --
src/mainboard/asus/f2a85-m/buildOpts.c | 144 ++++++++-----------------
src/mainboard/asus/f2a85-m/mptable.c | 1 -
src/mainboard/asus/f2a85-m_le/buildOpts.c | 140 +++++++-----------------
src/mainboard/asus/k8v-x/mptable.c | 28 ++---
src/mainboard/asus/k8v-x/romstage.c | 8 +-
src/mainboard/asus/kcma-d8/mptable.c | 2 +-
src/mainboard/asus/kcma-d8/resourcemap.c | 6 --
src/mainboard/asus/kcma-d8/romstage.c | 29 ++---
src/mainboard/asus/kfsn4-dre/get_bus_conf.c | 2 +-
src/mainboard/asus/kfsn4-dre/irq_tables.c | 6 +-
src/mainboard/asus/kfsn4-dre/mptable.c | 18 ++--
src/mainboard/asus/kfsn4-dre/resourcemap.c | 3 -
src/mainboard/asus/kfsn4-dre/romstage.c | 26 ++---
src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c | 3 -
src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c | 2 +-
src/mainboard/asus/kfsn4-dre_k8/irq_tables.c | 6 +-
src/mainboard/asus/kfsn4-dre_k8/mptable.c | 18 ++--
src/mainboard/asus/kfsn4-dre_k8/resourcemap.c | 3 -
src/mainboard/asus/kfsn4-dre_k8/romstage.c | 19 +---
src/mainboard/asus/kgpe-d16/mptable.c | 2 +-
src/mainboard/asus/kgpe-d16/resourcemap.c | 6 --
src/mainboard/asus/kgpe-d16/romstage.c | 38 +++----
src/mainboard/asus/m2n-e/get_bus_conf.c | 18 +---
src/mainboard/asus/m2n-e/resourcemap.c | 6 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 4 +-
src/mainboard/asus/m2v/romstage.c | 4 +-
src/mainboard/asus/m4a78-em/resourcemap.c | 12 +--
src/mainboard/asus/m4a78-em/romstage.c | 29 ++---
src/mainboard/asus/m4a785-m/resourcemap.c | 12 +--
src/mainboard/asus/m4a785-m/romstage.c | 29 ++---
src/mainboard/asus/m5a88-v/mainboard.c | 1 -
src/mainboard/asus/m5a88-v/platform_cfg.h | 2 -
src/mainboard/asus/m5a88-v/resourcemap.c | 10 +-
src/mainboard/asus/m5a88-v/romstage.c | 34 ++----
44 files changed, 244 insertions(+), 550 deletions(-)
diff --git a/src/mainboard/asus/a8n_e/get_bus_conf.c b/src/mainboard/asus/a8n_e/get_bus_conf.c
index ea2744a..4392e36 100644
--- a/src/mainboard/asus/a8n_e/get_bus_conf.c
+++ b/src/mainboard/asus/a8n_e/get_bus_conf.c
@@ -75,7 +75,7 @@ void get_bus_conf(void)
get_sblk_pci1234();
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */
sbdn = sysconf.sbdn;
for (i = 0; i < 6; i++)
diff --git a/src/mainboard/asus/a8n_e/irq_tables.c b/src/mainboard/asus/a8n_e/irq_tables.c
index 59d506d..96d90be 100644
--- a/src/mainboard/asus/a8n_e/irq_tables.c
+++ b/src/mainboard/asus/a8n_e/irq_tables.c
@@ -170,13 +170,8 @@ unsigned long write_pirq_routing_table(unsigned long addr)
pirq_info++;
slot_num++;
-#if 0
/* Firewire? */
- write_pirq_info(pirq_info, bus_ck804_1, (0x5 << 3) | 0, 0x3, 0xdeb8, 0,
- 0, 0, 0, 0, 0, 0, 0);
- pirq_info++;
- slot_num++;
-#endif
+
pirq->size = 32 + 16 * slot_num;
diff --git a/src/mainboard/asus/a8n_e/mptable.c b/src/mainboard/asus/a8n_e/mptable.c
index 73b1f15..111a8ac 100644
--- a/src/mainboard/asus/a8n_e/mptable.c
+++ b/src/mainboard/asus/a8n_e/mptable.c
@@ -73,17 +73,17 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
- // Onboard ck804 smbus
+ /* Onboard ck804 smbus */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
- // Onboard ck804 USB 1.1
+ /* Onboard ck804 USB 1.1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
- // Onboard ck804 USB 2
+ /* Onboard ck804 USB 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
@@ -92,17 +92,17 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 4) << 2) | 0, apicid_ck804, 0x3);
- // Onboard ck804 SATA 0
+ /* Onboard ck804 SATA 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
- // Onboard ck804 SATA 1
+ /* Onboard ck804 SATA 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
- // Onboard ck804 NIC
+ /* Onboard ck804 NIC */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 10) << 2) | 0, apicid_ck804,
0x17);
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index 4965c4f..abe6336 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -108,9 +108,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
-#endif
needs_reset = setup_coherent_ht_domain();
@@ -136,17 +133,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enable_smbus();
-#if 0
- dump_spd_registers(&ctrl[0]);
- dump_smbus_registers();
-#endif
-
- sdram_initialize(nodes, ctrl);
-
-#if 0
- print_pci_devices();
- dump_pci_devices();
-#endif
-
post_cache_as_ram();
}
diff --git a/src/mainboard/asus/a8v-e_deluxe/mptable.c b/src/mainboard/asus/a8v-e_deluxe/mptable.c
index f3d3d06..e54c4de 100644
--- a/src/mainboard/asus/a8v-e_deluxe/mptable.c
+++ b/src/mainboard/asus/a8v-e_deluxe/mptable.c
@@ -39,20 +39,20 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); /* IRQ17 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); /* IRQ17 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); /* IRQ17 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index b8f631b..cb4f63b 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -136,10 +136,10 @@ static void sio_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // Node 1
+ /* Node 1 */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
diff --git a/src/mainboard/asus/a8v-e_se/mptable.c b/src/mainboard/asus/a8v-e_se/mptable.c
index f3d3d06..e54c4de 100644
--- a/src/mainboard/asus/a8v-e_se/mptable.c
+++ b/src/mainboard/asus/a8v-e_se/mptable.c
@@ -39,20 +39,20 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); /* IRQ17 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); /* IRQ17 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); /* IRQ17 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 4c74d0f..ab9a037 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -136,10 +136,10 @@ static void sio_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM2, 0, 0,
0, 0, 0, 0,
- // Node 1
+ /* Node 1 */
DIMM1, DIMM3, 0, 0,
0, 0, 0, 0,
};
diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c
index 6348d5a..f0e5752 100644
--- a/src/mainboard/asus/f2a85-m/OemCustomize.c
+++ b/src/mainboard/asus/f2a85-m/OemCustomize.c
@@ -96,19 +96,19 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = {
* Untested: HDMI
*/
static const PCIe_DDI_DESCRIPTOR DdiList [] = {
- // DP0 to HDMI0/DP
+ /* DP0 to HDMI0/DP */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1)
},
- // DP1 to FCH
+ /* DP1 to FCH */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2)
},
- // DP2 to HDMI1/DP
+ /* DP2 to HDMI1/DP */
{
0,
PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35),
@@ -148,11 +148,10 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly)
ALLOCATE_HEAP_PARAMS AllocHeapParams;
- // GNB PCIe topology Porting
+ /* GNB PCIe topology Porting */
+
+ /* Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR */
- //
- // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR
- //
AllocHeapParams.RequestedBufferSize = sizeof(Trinity) + sizeof(PortList) + sizeof(DdiList);
AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START;
AllocHeapParams.Persist = HEAP_LOCAL_CACHE;
diff --git a/src/mainboard/asus/f2a85-m/OptionsIds.h b/src/mainboard/asus/f2a85-m/OptionsIds.h
index b45f5a8..0717812 100644
--- a/src/mainboard/asus/f2a85-m/OptionsIds.h
+++ b/src/mainboard/asus/f2a85-m/OptionsIds.h
@@ -42,18 +42,8 @@
*
**/
-//#define IDSOPT_IDS_ENABLED TRUE
-//#define IDSOPT_CONTROL_ENABLED TRUE
#define IDSOPT_TRACING_ENABLED TRUE
#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
-//#define IDSOPT_PERF_ANALYSIS TRUE
#define IDSOPT_ASSERT_ENABLED TRUE
-//#undef IDSOPT_DEBUG_ENABLED
-//#define IDSOPT_DEBUG_ENABLED FALSE
-//#undef IDSOPT_HOST_SIMNOW
-//#define IDSOPT_HOST_SIMNOW FALSE
-//#undef IDSOPT_HOST_HDT
-//#define IDSOPT_HOST_HDT FALSE
-//#define IDS_DEBUG_PORT 0x80
#endif
diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c
index e0a1ea4..704ec9c 100644
--- a/src/mainboard/asus/f2a85-m/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m/buildOpts.c
@@ -63,37 +63,26 @@
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
-#define BLDOPT_REMOVE_SRAT FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_DMI TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+/* This element selects whether P-States should be forced to be independent,
+ * as reported by the ACPI _PSD object. For single-link processors,
+ * setting TRUE for OS to support this feature.
+ */
+
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
/* Build configuration values here.
@@ -140,7 +129,7 @@
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
#define BLDOPT_REMOVE_ALIB FALSE
@@ -152,16 +141,9 @@
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
#define BLDCFG_CFG_ABM_SUPPORT 0
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
-
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+/* Specify the default values for the VRM controlling the VDDNB plane.
+ * If not specified, the values used for the core VRM will be applied
+*/
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
@@ -171,17 +153,13 @@
#if CONFIG_GFXUMA
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* 512M */
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT TRUE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
@@ -189,43 +167,6 @@
/*
* Customized OEM build configurations for FCH component
*/
-// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
-// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
-// #define BLDCFG_AZALIA_SSID 0x780D1022
-// #define BLDCFG_SMBUS_SSID 0x780B1022
-// #define BLDCFG_IDE_SSID 0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID 0x78011022
-// #define BLDCFG_SATA_IDE_SSID 0x78001022
-// #define BLDCFG_SATA_RAID5_SSID 0x78031022
-// #define BLDCFG_SATA_RAID_SSID 0x78021022
-// #define BLDCFG_EHCI_SSID 0x78081022
-// #define BLDCFG_OHCI_SSID 0x78071022
-// #define BLDCFG_LPC_SSID 0x780E1022
-// #define BLDCFG_SD_SSID 0x78061022
-// #define BLDCFG_XHCI_SSID 0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
@@ -245,40 +186,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 /* DDR 400 */
+#define DDR533_FREQUENCY 266 /* DDR 533 */
+#define DDR667_FREQUENCY 333 /* DDR 667 */
+#define DDR800_FREQUENCY 400 /* DDR 800 */
+#define DDR1066_FREQUENCY 533 /* DDR 1066 */
+#define DDR1333_FREQUENCY 667 /* DDR 1333 */
+#define DDR1600_FREQUENCY 800 /* DDR 1600 */
+#define DDR1866_FREQUENCY 933 /* DDR 1866 */
+#define DDR2100_FREQUENCY 1050 /* DDR 2100 */
+#define DDR2133_FREQUENCY 1066 /* DDR 2133 */
+#define DDR2400_FREQUENCY 1200 /* DDR 2400 */
+#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 /* Use best rate possible */
+#define TIMING_MODE_LIMITED 1 /* Set user top limit */
+#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */
/*
* Agesa optional capabilities selection.
@@ -324,17 +265,16 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-//#define BLDCFG_IR_PIN_CONTROL 0x33
-//#define FCH_NO_XHCI_SUPPORT FALSE
+
GPIO_CONTROL f2a85_m_gpio[] = {
-// {183, Function1, PullUpB},
{-1}
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c
index 09d9455..5ff459b 100644
--- a/src/mainboard/asus/f2a85-m/mptable.c
+++ b/src/mainboard/asus/f2a85-m/mptable.c
@@ -81,7 +81,6 @@ static void *smp_write_config_table(void *v)
smp_write_processors(mc);
- //mptable_write_buses(mc, NULL, &bus_isa);
my_smp_write_bus(mc, 0, "PCI ");
my_smp_write_bus(mc, 1, "PCI ");
bus_isa = 0x02;
diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c
index 88ff778..5e5581c 100644
--- a/src/mainboard/asus/f2a85-m_le/buildOpts.c
+++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c
@@ -63,36 +63,24 @@
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_SODIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
-//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
-//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
-//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
-//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
-#define BLDOPT_REMOVE_SRAT FALSE //TRUE
-#define BLDOPT_REMOVE_SLIT FALSE //TRUE
-#define BLDOPT_REMOVE_WHEA FALSE //TRUE
+#define BLDOPT_REMOVE_SRAT FALSE
+#define BLDOPT_REMOVE_SLIT FALSE
+#define BLDOPT_REMOVE_WHEA FALSE
#define BLDOPT_REMOVE_CRAT TRUE
#define BLDOPT_REMOVE_DMI TRUE
-//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
-//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
-//This element selects whether P-States should be forced to be independent,
-// as reported by the ACPI _PSD object. For single-link processors,
-// setting TRUE for OS to support this feature.
-
-//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
+/* This element selects whether P-States should be forced to be independent,
+ * as reported by the ACPI _PSD object. For single-link processors,
+ * setting TRUE for OS to support this feature.
+ */
#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
@@ -140,7 +128,7 @@
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
#define BLDCFG_1GB_ALIGN FALSE
#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
-#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 // PCIE Spread Spectrum default value 0.36%
+#define BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM 36 /* PCIE Spread Spectrum default value 0.36% */
#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770
#define BLDOPT_REMOVE_ALIB FALSE
@@ -152,16 +140,9 @@
#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL 200
#define BLDCFG_CFG_ABM_SUPPORT 0
-//#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
-
-// Specify the default values for the VRM controlling the VDDNB plane.
-// If not specified, the values used for the core VRM will be applied
-//#define BLDCFG_VRM_NB_CURRENT_LIMIT 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 1 // Zero - disable NBPSI_L, Non-zero - enable NBPSI_L
-//#define BLDCFG_VRM_NB_SLEW_RATE 5000 // Used in calculating the VSRampSlamTime
-//#define BLDCFG_VRM_NB_ADDITIONAL_DELAY 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_HIGH_SPEED_ENABLE 0 // Not currently used on Trinity
-//#define BLDCFG_VRM_NB_INRUSH_CURRENT_LIMIT 0 // Not currently used on Trinity
+/* Specify the default values for the VRM controlling the VDDNB plane.
+ * If not specified, the values used for the core VRM will be applied
+ */
#define BLDCFG_VRM_NB_CURRENT_LIMIT 60000
@@ -171,17 +152,13 @@
#if CONFIG_GFXUMA
#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
#define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED
-//#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/
-#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000//512M
+#define BLDCFG_UMA_ALLOCATION_SIZE 0x2000 /* 512M */
#define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE
#endif
#define BLDCFG_IOMMU_SUPPORT FALSE
#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
-//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
-//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
-//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
/* Process the options...
* This file include MUST occur AFTER the user option selection settings
@@ -189,43 +166,6 @@
/*
* Customized OEM build configurations for FCH component
*/
-// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
-// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
-// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
-// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
-// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
-// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
-// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
-// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
-// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
-// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
-// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
-// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
-// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
-// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
-// #define BLDCFG_AZALIA_SSID 0x780D1022
-// #define BLDCFG_SMBUS_SSID 0x780B1022
-// #define BLDCFG_IDE_SSID 0x780C1022
-// #define BLDCFG_SATA_AHCI_SSID 0x78011022
-// #define BLDCFG_SATA_IDE_SSID 0x78001022
-// #define BLDCFG_SATA_RAID5_SSID 0x78031022
-// #define BLDCFG_SATA_RAID_SSID 0x78021022
-// #define BLDCFG_EHCI_SSID 0x78081022
-// #define BLDCFG_OHCI_SSID 0x78071022
-// #define BLDCFG_LPC_SSID 0x780E1022
-// #define BLDCFG_SD_SSID 0x78061022
-// #define BLDCFG_XHCI_SSID 0x78121022
-// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
-// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
-// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
-// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
-// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
-// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
{
@@ -245,40 +185,40 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList
- // This is the delivery package title, "BrazosPI"
- // This string MUST be exactly 8 characters long
+ /* This is the delivery package title, "BrazosPI" */
+ /* This string MUST be exactly 8 characters long */
#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
- // This is the release version number of the AGESA component
- // This string MUST be exactly 12 characters long
+ /* This is the release version number of the AGESA component */
+ /* This string MUST be exactly 12 characters long */
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
/* MEMORY_BUS_SPEED */
-#define DDR400_FREQUENCY 200 ///< DDR 400
-#define DDR533_FREQUENCY 266 ///< DDR 533
-#define DDR667_FREQUENCY 333 ///< DDR 667
-#define DDR800_FREQUENCY 400 ///< DDR 800
-#define DDR1066_FREQUENCY 533 ///< DDR 1066
-#define DDR1333_FREQUENCY 667 ///< DDR 1333
-#define DDR1600_FREQUENCY 800 ///< DDR 1600
-#define DDR1866_FREQUENCY 933 ///< DDR 1866
-#define DDR2100_FREQUENCY 1050 ///< DDR 2100
-#define DDR2133_FREQUENCY 1066 ///< DDR 2133
-#define DDR2400_FREQUENCY 1200 ///< DDR 2400
-#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+#define DDR400_FREQUENCY 200 /* DDR 400 */
+#define DDR533_FREQUENCY 266 /* DDR 533 */
+#define DDR667_FREQUENCY 333 /* DDR 667 */
+#define DDR800_FREQUENCY 400 /* DDR 800 */
+#define DDR1066_FREQUENCY 533 /* DDR 1066 */
+#define DDR1333_FREQUENCY 667 /* DDR 1333 */
+#define DDR1600_FREQUENCY 800 /* DDR 1600 */
+#define DDR1866_FREQUENCY 933 /* DDR 1866 */
+#define DDR2100_FREQUENCY 1050 /* DDR 2100 */
+#define DDR2133_FREQUENCY 1066 /* DDR 2133 */
+#define DDR2400_FREQUENCY 1200 /* DDR 2400 */
+#define UNSUPPORTED_DDR_FREQUENCY 1201 /* Highest limit of DDR frequency */
/* QUANDRANK_TYPE*/
-#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
-#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+#define QUADRANK_REGISTERED 0 /* Quadrank registered DIMM */
+#define QUADRANK_UNBUFFERED 1 /* Quadrank unbuffered DIMM */
/* USER_MEMORY_TIMING_MODE */
-#define TIMING_MODE_AUTO 0 ///< Use best rate possible
-#define TIMING_MODE_LIMITED 1 ///< Set user top limit
-#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+#define TIMING_MODE_AUTO 0 /* Use best rate possible */
+#define TIMING_MODE_LIMITED 1 /* Set user top limit */
+#define TIMING_MODE_SPECIFIC 2 /* Set user specified speed */
/* POWER_DOWN_MODE */
-#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
-#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_BY_CHANNEL 0 /* Channel power down mode */
+#define POWER_DOWN_BY_CHIP_SELECT 1 /* Chip select power down mode */
/*
* Agesa optional capabilities selection.
@@ -324,17 +264,15 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] =
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
-//#define BLDCFG_IR_PIN_CONTROL 0x33
-//#define FCH_NO_XHCI_SUPPORT FALSE
GPIO_CONTROL f2a85_m_gpio[] = {
-// {183, Function1, PullUpB},
{-1}
};
#define BLDCFG_FCH_GPIO_CONTROL_LIST (&f2a85_m_gpio[0])
-// The following definitions specify the default values for various parameters in which there are
-// no clearly defined defaults to be used in the common file. The values below are based on product
-// and BKDG content, please consult the AGESA Memory team for consultation.
+/* The following definitions specify the default values for various parameters in which there are
+ * no clearly defined defaults to be used in the common file. The values below are based on product
+ * and BKDG content, please consult the AGESA Memory team for consultation.
+ */
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
diff --git a/src/mainboard/asus/k8v-x/mptable.c b/src/mainboard/asus/k8v-x/mptable.c
index 8525b02..7f20bde 100644
--- a/src/mainboard/asus/k8v-x/mptable.c
+++ b/src/mainboard/asus/k8v-x/mptable.c
@@ -39,20 +39,20 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); //IRQ19
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); //IRQ17
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); //IRQ16
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); //IRQ18
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); //IRQ19
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); //IRQ16
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); //IRQ17
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 0, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 1, VT8237R_APIC_ID, 0x11); /* IRQ17 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 2, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xb << 2) | 3, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 0, VT8237R_APIC_ID, 0x11); /* IRQ17 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 1, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 2, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xc << 2) | 3, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 0, VT8237R_APIC_ID, 0x12); /* IRQ18 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 1, VT8237R_APIC_ID, 0x13); /* IRQ19 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 2, VT8237R_APIC_ID, 0x10); /* IRQ16 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xd << 2) | 3, VT8237R_APIC_ID, 0x11); /* IRQ17 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x14);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x0, (0xf << 2) | 1, VT8237R_APIC_ID, 0x14);
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index 0f98062..87baf44 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -92,10 +92,10 @@ unsigned int get_sbdn(unsigned bus)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM1, DIMM2, 0,
0, 0, 0, 0,
- // Node 1
+ /* Node 1 */
0, 0, 0, 0,
0, 0, 0, 0,
};
@@ -169,8 +169,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
unsigned char mask;
mask = 0;
-// mask |= 1 /* AGP voltage 1.7 V (not verified, just vendor BIOS value) */
-// mask |= 2 /* V-Link voltage 2.6 V (not verified either) */
+ /* mask |= 1 AGP voltage 1.7 V (not verified, just vendor BIOS value) */
+ /* mask |= 2 V-Link voltage 2.6 V (not verified either) */
smbus_write_byte(0x4a, 0x00, (smbus_read_byte(0x4a, 0x00) & ~0x0f) | (0x0f ^ (mask << 2)));
smbus_write_byte(0x4a, 0x01, (smbus_read_byte(0x4a, 0x01) & ~0x03) | (0x03 ^ mask));
diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c
index aff077a..f102c64 100644
--- a/src/mainboard/asus/kcma-d8/mptable.c
+++ b/src/mainboard/asus/kcma-d8/mptable.c
@@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v)
uint16_t word;
uint8_t byte;
- sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
+ sp5100_bus_number = 0; /* bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. */
dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
if (dev) {
diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c
index 937f4b7..3f46010 100644
--- a/src/mainboard/asus/kcma-d8/resourcemap.c
+++ b/src/mainboard/asus/kcma-d8/resourcemap.c
@@ -47,7 +47,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -86,7 +85,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -226,7 +224,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -302,7 +299,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -341,7 +337,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -481,7 +476,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c
index 256cf7e..a927198 100644
--- a/src/mainboard/asus/kcma-d8/romstage.c
+++ b/src/mainboard/asus/kcma-d8/romstage.c
@@ -39,7 +39,6 @@
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <cpu/x86/bist.h>
#include <smp/spinlock.h>
-// #include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include <southbridge/amd/sr5650/sr5650.h>
@@ -95,16 +94,16 @@ static void switch_spd_mux(uint8_t channel)
}
static const uint8_t spd_addr_fam15[] = {
- // Socket 0 Node 0 ("Node 0")
+ /* Socket 0 Node 0 ("Node 0") */
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
- // Socket 1 Node 0 ("Node 1")
+ /* Socket 1 Node 0 ("Node 1") */
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
};
static const uint8_t spd_addr_fam10[] = {
- // Socket 0 Node 0 ("Node 0")
+ /* Socket 0 Node 0 ("Node 0") */
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
- // Socket 1 Node 0 ("Node 1")
+ /* Socket 1 Node 0 ("Node 1") */
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
};
@@ -489,10 +488,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
#if IS_ENABLED(CONFIG_SET_FIDVID)
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
#endif
@@ -505,7 +504,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
- init_timer(); // Need to use TMICT to synconize FID/VID
+ init_timer(); /* Need to use TMICT to synconize FID/VID */
sr5650_htinit();
@@ -544,16 +543,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10);
post_code(0x3D);
-#if 0
- /* FIXME
- * After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
- */
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
- }
-#endif
post_code(0x40);
@@ -588,8 +577,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
index 435731d..6d6dfe7 100644
--- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c
@@ -85,7 +85,7 @@ void get_bus_conf(void)
get_pci1234();
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */
sbdn = sysconf.sbdn;
for (i = 0; i < 6; i++)
diff --git a/src/mainboard/asus/kfsn4-dre/irq_tables.c b/src/mainboard/asus/kfsn4-dre/irq_tables.c
index 0a990a7..2038b66 100644
--- a/src/mainboard/asus/kfsn4-dre/irq_tables.c
+++ b/src/mainboard/asus/kfsn4-dre/irq_tables.c
@@ -19,9 +19,9 @@
* GNU General Public License for more details.
*/
-// WARNING
-// These tables are INVALID for this mainboard!
-// The ACPI tables are correct; a backport to these PIR tables is needed...
+/* WARNING */
+/* These tables are INVALID for this mainboard! */
+/* The ACPI tables are correct; a backport to these PIR tables is needed... */
#include <console/console.h>
#include <device/pci.h>
diff --git a/src/mainboard/asus/kfsn4-dre/mptable.c b/src/mainboard/asus/kfsn4-dre/mptable.c
index cdf86a1..61438f9 100644
--- a/src/mainboard/asus/kfsn4-dre/mptable.c
+++ b/src/mainboard/asus/kfsn4-dre/mptable.c
@@ -18,9 +18,9 @@
* GNU General Public License for more details.
*/
-// WARNING
-// These tables are INCOMPLETE for this mainboard!
-// The ACPI tables are correct; a backport to these MP tables is needed...
+/* WARNING */
+/* These tables are INCOMPLETE for this mainboard! */
+/* The ACPI tables are correct; a backport to these MP tables is needed... */
#include <console/console.h>
#include <arch/smp/mpspec.h>
@@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v)
f - irq 15
*/
- // Enable interrupts for commonly used devices (USB, SATA, etc.)
+ /* Enable interrupts for commonly used devices (USB, SATA, etc.) */
pci_write_config32(dev, 0x7c, 0x0d800018);
pci_write_config32(dev, 0x80, 0xd8002009);
pci_write_config32(dev, 0x84, 0x00000001);
@@ -112,27 +112,27 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
- // Onboard ck804 smbus
+ /* Onboard ck804 smbus */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
- // Onboard ck804 USB 1.1
+ /* Onboard ck804 USB 1.1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
- // Onboard ck804 USB 2
+ /* Onboard ck804 USB 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
- // Onboard ck804 SATA 0
+ /* Onboard ck804 SATA 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
- // Onboard ck804 SATA 1
+ /* Onboard ck804 SATA 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
diff --git a/src/mainboard/asus/kfsn4-dre/resourcemap.c b/src/mainboard/asus/kfsn4-dre/resourcemap.c
index cfbade6..984cd07 100644
--- a/src/mainboard/asus/kfsn4-dre/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre/resourcemap.c
@@ -47,7 +47,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -86,7 +85,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -226,7 +224,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c
index c7fa429..e029d10 100644
--- a/src/mainboard/asus/kfsn4-dre/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre/romstage.c
@@ -44,7 +44,6 @@ unsigned int get_sbdn(unsigned bus);
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627thg/w83627thg.h>
#include <cpu/x86/bist.h>
-// #include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdfam10/debug.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
@@ -176,9 +175,9 @@ static void sio_setup(void)
}
static const uint8_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
RC00, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
- // Node 1
+ /* Node 1 */
RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7,
};
@@ -268,10 +267,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -294,7 +293,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
- init_timer(); // Need to use TMICT to synconize FID/VID
+ init_timer(); /* Need to use TMICT to synconize FID/VID */
wants_reset = ck804_early_setup_x();
@@ -319,17 +318,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
-#if 0
- /* FIXME
- * After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
- */
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
- }
-#endif
-
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
@@ -364,8 +352,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Restore default SuperIO access */
outb(0xaa, port);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c b/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
index c6d2981..24cbbe3 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/acpi_tables.c
@@ -49,9 +49,6 @@ unsigned long acpi_fill_madt(unsigned long current)
pci_write_config32(dev, 0x84, 0x00000001);
}
-// /* IRQ of timer (override IRQ0 --> APIC IRQ2) */
-// current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-// current, 0, 0, 2, 0);
/* IRQ9 */
current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
diff --git a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
index 101997a..1770e83 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/get_bus_conf.c
@@ -74,7 +74,7 @@ void get_bus_conf(void)
get_sblk_pci1234();
- sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
+ sysconf.sbdn = (sysconf.hcdn[0] & 0xff); /* first byte of first chain */
sbdn = sysconf.sbdn;
for (i = 0; i < 6; i++)
diff --git a/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c b/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
index d06980c..8e01431 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/irq_tables.c
@@ -19,9 +19,9 @@
* GNU General Public License for more details.
*/
-// WARNING
-// These tables are INVALID for this mainboard!
-// The ACPI tables are correct; a backport to these PIR tables is needed...
+/* WARNING */
+/* These tables are INVALID for this mainboard! */
+/* The ACPI tables are correct; a backport to these PIR tables is needed... */
#include <console/console.h>
#include <device/pci.h>
diff --git a/src/mainboard/asus/kfsn4-dre_k8/mptable.c b/src/mainboard/asus/kfsn4-dre_k8/mptable.c
index 21a433a..7dde203 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/mptable.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/mptable.c
@@ -18,9 +18,9 @@
* GNU General Public License for more details.
*/
-// WARNING
-// These tables are INCOMPLETE for this mainboard!
-// The ACPI tables are correct; a backport to these MP tables is needed...
+/* WARNING */
+/* These tables are INCOMPLETE for this mainboard! */
+/* The ACPI tables are correct; a backport to these MP tables is needed... */
#include <console/console.h>
#include <arch/smp/mpspec.h>
@@ -103,7 +103,7 @@ static void *smp_write_config_table(void *v)
f - irq 15
*/
- // Enable interrupts for commonly used devices (USB, SATA, etc.)
+ /* Enable interrupts for commonly used devices (USB, SATA, etc.) */
pci_write_config32(dev, 0x7c, 0x0d800018);
pci_write_config32(dev, 0x80, 0xd8002009);
pci_write_config32(dev, 0x84, 0x00000001);
@@ -112,27 +112,27 @@ static void *smp_write_config_table(void *v)
mptable_add_isa_interrupts(mc, bus_isa, apicid_ck804, 0);
- // Onboard ck804 smbus
+ /* Onboard ck804 smbus */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 1) << 2) | 1, apicid_ck804,
0xa);
- // Onboard ck804 USB 1.1
+ /* Onboard ck804 USB 1.1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 0, apicid_ck804,
0x15);
- // Onboard ck804 USB 2
+ /* Onboard ck804 USB 2 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 2) << 2) | 1, apicid_ck804,
0x14);
- // Onboard ck804 SATA 0
+ /* Onboard ck804 SATA 0 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 7) << 2) | 0, apicid_ck804,
0x17);
- // Onboard ck804 SATA 1
+ /* Onboard ck804 SATA 1 */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW,
bus_ck804[0], ((sbdn + 8) << 2) | 0, apicid_ck804,
0x16);
diff --git a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
index cfbade6..984cd07 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/resourcemap.c
@@ -47,7 +47,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -86,7 +85,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -226,7 +224,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
index 03a095d..0096455 100644
--- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c
+++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c
@@ -174,9 +174,9 @@ static void sio_setup(void)
}
static const uint16_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
RC00 | DIMM0, RC00 | DIMM2, RC00 | DIMM4, RC00 | DIMM6, RC00 | DIMM1, RC00 | DIMM3, RC00 | DIMM5, RC00 | DIMM7,
- // Node 1
+ /* Node 1 */
RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7,
};
@@ -317,17 +317,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "enable_smbus()\n");
enable_smbus();
-#if 0
- /* FIXME
- * After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
- */
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
- }
-#endif
-
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
@@ -361,6 +350,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Restore default SuperIO access */
outb(0xaa, port);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c
index a55101d..3430fcd 100644
--- a/src/mainboard/asus/kgpe-d16/mptable.c
+++ b/src/mainboard/asus/kgpe-d16/mptable.c
@@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v)
uint16_t word;
uint8_t byte;
- sp5100_bus_number = 0; //bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0.
+ sp5100_bus_number = 0; /* bus_sp5100[0]; TODO: why bus_sp5100[0] use same value of bus_sr5650[0] assigned by get_pci1234(), instead of 0. */
dev = dev_find_slot(sp5100_bus_number, PCI_DEVFN(sbdn_sp5100 + 0x14, 0));
if (dev) {
diff --git a/src/mainboard/asus/kgpe-d16/resourcemap.c b/src/mainboard/asus/kgpe-d16/resourcemap.c
index d1fcad7..0d9872d 100644
--- a/src/mainboard/asus/kgpe-d16/resourcemap.c
+++ b/src/mainboard/asus/kgpe-d16/resourcemap.c
@@ -47,7 +47,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -86,7 +85,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -226,7 +224,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -302,7 +299,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -341,7 +337,6 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
- // PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -481,7 +476,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00001013,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c
index 80d1c45..6689d3e 100644
--- a/src/mainboard/asus/kgpe-d16/romstage.c
+++ b/src/mainboard/asus/kgpe-d16/romstage.c
@@ -39,7 +39,6 @@
#include <superio/winbond/w83667hg-a/w83667hg-a.h>
#include <cpu/x86/bist.h>
#include <smp/spinlock.h>
-// #include "northbridge/amd/amdk8/incoherent_ht.c"
#include <southbridge/amd/sb700/sb700.h>
#include <southbridge/amd/sb700/smbus.h>
#include <southbridge/amd/sr5650/sr5650.h>
@@ -95,24 +94,24 @@ static void switch_spd_mux(uint8_t channel)
}
static const uint8_t spd_addr_fam15[] = {
- // Socket 0 Node 0 ("Node 0")
+ /* Socket 0 Node 0 ("Node 0") */
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
- // Socket 0 Node 1 ("Node 1")
+ /* Socket 0 Node 1 ("Node 1") */
RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
- // Socket 1 Node 0 ("Node 2")
+ /* Socket 1 Node 0 ("Node 2") */
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
- // Socket 1 Node 1 ("Node 3")
+ /* Socket 1 Node 1 ("Node 3") */
RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
};
static const uint8_t spd_addr_fam10[] = {
- // Socket 0 Node 0 ("Node 0")
+ /* Socket 0 Node 0 ("Node 0") */
RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
- // Socket 0 Node 1 ("Node 1")
+ /* Socket 0 Node 1 ("Node 1") */
RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
- // Socket 1 Node 1 ("Node 2")
+ /* Socket 1 Node 1 ("Node 2") */
RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0,
- // Socket 1 Node 0 ("Node 3")
+ /* Socket 1 Node 0 ("Node 3") */
RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0,
};
@@ -530,10 +529,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
#if IS_ENABLED(CONFIG_SET_FIDVID)
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
#endif
@@ -546,7 +545,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
- init_timer(); // Need to use TMICT to synconize FID/VID
+ init_timer(); /* Need to use TMICT to synconize FID/VID */
sr5650_htinit();
@@ -585,17 +584,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam10);
post_code(0x3D);
-#if 0
- /* FIXME
- * After the AMD K10 code has been converted to use
- * IS_ENABLED(CONFIG_DEBUG_SMBUS) uncomment this block
- */
- if (IS_ENABLED(CONFIG_DEBUG_SMBUS)) {
- dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
- }
-#endif
-
post_code(0x40);
timestamp_add_now(TS_BEFORE_INITRAM);
@@ -629,8 +617,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x56, 0x0bb0);
pci_write_config16(PCI_DEV(0, 0x14, 0), 0x5a, 0x0ff0);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/asus/m2n-e/get_bus_conf.c b/src/mainboard/asus/m2n-e/get_bus_conf.c
index e56072a..ace7d55 100644
--- a/src/mainboard/asus/m2n-e/get_bus_conf.c
+++ b/src/mainboard/asus/m2n-e/get_bus_conf.c
@@ -25,8 +25,8 @@
#include <stdlib.h>
/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
-// busnum is default.
-unsigned char bus_mcp55[8]; // 1
+/* busnum is default. */
+unsigned char bus_mcp55[8]; /* 1 */
unsigned apicid_mcp55;
unsigned pci1234x[] = {
@@ -35,13 +35,6 @@ unsigned pci1234x[] = {
* please refer to * src/northbridge/amd/amdk8/get_sblk_pci1234.c.
*/
0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
};
unsigned hcdnx[] = {
@@ -49,13 +42,6 @@ unsigned hcdnx[] = {
* device in chain, assume every chain only have 4 ht device at most.
*/
0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
};
static unsigned get_bus_conf_done = 0;
diff --git a/src/mainboard/asus/m2n-e/resourcemap.c b/src/mainboard/asus/m2n-e/resourcemap.c
index 57e7389..f963d55 100644
--- a/src/mainboard/asus/m2n-e/resourcemap.c
+++ b/src/mainboard/asus/m2n-e/resourcemap.c
@@ -132,7 +132,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -167,7 +166,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -194,7 +192,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x00007000,
PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -224,7 +221,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000033,
PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -265,7 +261,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration region i
*/
-// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */
+ /* link 0 of CPU 0 --> Nvidia MCP55 */
PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index daf0b50..1fdbee4 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -111,10 +111,10 @@ unsigned int get_sbdn(unsigned bus)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // Node 1
+ /* Node 1 */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index c61557b..42c062c 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -208,10 +208,10 @@ static void m2v_bus_init(void)
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // Node 0
+ /* Node 0 */
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
- // Node 1
+ /* Node 1 */
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
};
diff --git a/src/mainboard/asus/m4a78-em/resourcemap.c b/src/mainboard/asus/m4a78-em/resourcemap.c
index 95d009a..d696c4d 100644
--- a/src/mainboard/asus/m4a78-em/resourcemap.c
+++ b/src/mainboard/asus/m4a78-em/resourcemap.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-
-
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
@@ -45,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -83,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ /* don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -131,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -166,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -193,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -223,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -264,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 6c081d4..6fc731c 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -13,11 +13,9 @@
* GNU General Public License for more details.
*/
-//#define SYSTEM_TYPE 0 /* SERVER */
-#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
+#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */
-//used by incoherent_ht
+/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@@ -104,12 +102,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -168,10 +164,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -198,8 +194,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-// die("Die Before MCT init.");
-
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@@ -210,21 +204,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// die("After MCT init before CAR disabled.");
-
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/asus/m4a785-m/resourcemap.c b/src/mainboard/asus/m4a785-m/resourcemap.c
index 95d009a..d696c4d 100644
--- a/src/mainboard/asus/m4a785-m/resourcemap.c
+++ b/src/mainboard/asus/m4a785-m/resourcemap.c
@@ -13,8 +13,6 @@
* GNU General Public License for more details.
*/
-
-
static void setup_mb_resource_map(void)
{
static const unsigned int register_values[] = {
@@ -45,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -83,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ /* don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -131,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -166,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -193,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -223,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -264,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index 2393e38..ec3b750 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -13,11 +13,9 @@
* GNU General Public License for more details.
*/
-//#define SYSTEM_TYPE 0 /* SERVER */
-#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
+#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */
-//used by incoherent_ht
+/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@@ -104,12 +102,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -168,10 +164,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -198,8 +194,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-// die("Die Before MCT init.");
-
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@@ -210,21 +204,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// die("After MCT init before CAR disabled.");
-
rs780_before_pci_init();
sb7xx_51xx_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
diff --git a/src/mainboard/asus/m5a88-v/mainboard.c b/src/mainboard/asus/m5a88-v/mainboard.c
index 941ba26..e45f48e 100644
--- a/src/mainboard/asus/m5a88-v/mainboard.c
+++ b/src/mainboard/asus/m5a88-v/mainboard.c
@@ -22,7 +22,6 @@
#include <device/pci_def.h>
#include "SBPLATFORM.h"
-
u8 is_dev3_present(void);
void set_pcie_dereset(void);
void set_pcie_reset(void);
diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h
index 161b106..2516e7a 100644
--- a/src/mainboard/asus/m5a88-v/platform_cfg.h
+++ b/src/mainboard/asus/m5a88-v/platform_cfg.h
@@ -13,7 +13,6 @@
* GNU General Public License for more details.
*/
-
#ifndef _PLATFORM_CFG_H_
#define _PLATFORM_CFG_H_
@@ -161,7 +160,6 @@
* SDIN2 is define at BIT4 & BIT5
* SDIN3 is define at BIT6 & BIT7
*/
-//#define AZALIA_SDIN_PIN 0xAA
#define AZALIA_SDIN_PIN 0x2A
/**
diff --git a/src/mainboard/asus/m5a88-v/resourcemap.c b/src/mainboard/asus/m5a88-v/resourcemap.c
index 2978bab..4f2c074 100644
--- a/src/mainboard/asus/m5a88-v/resourcemap.c
+++ b/src/mainboard/asus/m5a88-v/resourcemap.c
@@ -43,7 +43,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40 bit address
* that define the end of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x44), 0x0000f8f8, 0x00000000, // Don't touch it, we need it for CONFIG_CAR_FAM10
+ /* Don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x4C), 0x0000f8f8, 0x00000001,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x54), 0x0000f8f8, 0x00000002,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x5C), 0x0000f8f8, 0x00000003,
@@ -81,7 +81,7 @@ static void setup_mb_resource_map(void)
* This field defines the upper address bits of a 40-bit address
* that define the start of the DRAM region.
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x40), 0x0000f8fc, 0x00000000,// don't touch it, we need it for CONFIG_CAR_FAM10
+ /* don't touch it, we need it for CONFIG_CAR_FAM10 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x48), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x50), 0x0000f8fc, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0x58), 0x0000f8fc, 0x00000000,
@@ -129,7 +129,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA4), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xAC), 0x00000048, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB4), 0x00000048, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xBC), 0x00000048, 0x00ffff00,
/* Memory-Mapped I/O Base i Registers
* F1:0x80 i = 0
@@ -164,7 +163,6 @@ static void setup_mb_resource_map(void)
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA0), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xA8), 0x000000f0, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB0), 0x000000f0, 0x00000000,
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xB8), 0x000000f0, 0x00fc0003,
/* PCI I/O Limit i Registers
* F1:0xC4 i = 0
@@ -191,7 +189,6 @@ static void setup_mb_resource_map(void)
* This field defines the end of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x01fff000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000,
@@ -221,7 +218,6 @@ static void setup_mb_resource_map(void)
* This field defines the start of PCI I/O region n
* [31:25] Reserved
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC0), 0xFE000FCC, 0x00000003,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC8), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD0), 0xFE000FCC, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD8), 0xFE000FCC, 0x00000000,
@@ -262,7 +258,7 @@ static void setup_mb_resource_map(void)
* [31:24] Bus Number Limit i
* This field defines the highest bus number in configuration regin i
*/
-// PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x06000003, // AMD 8111 on link0 of CPU 0
+ /* AMD 8111 on link0 of CPU 0 */
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000,
PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000,
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index 28867ee..5fd16ff 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -13,11 +13,9 @@
* GNU General Public License for more details.
*/
-//#define SYSTEM_TYPE 0 /* SERVER */
-#define SYSTEM_TYPE 1 /* DESKTOP */
-//#define SYSTEM_TYPE 2 /* MOBILE */
+#define SYSTEM_TYPE 1 /* SERVER=0, DESKTOP=1, MOBILE=2 */
-//used by incoherent_ht
+/* used by incoherent_ht */
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
@@ -85,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
- //enable port80 decoding and southbridge poweron init
+ /*enable port80 decoding and southbridge poweron init */
sb_Poweron_Init();
}
@@ -105,12 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
printk(BIOS_DEBUG, "\n");
-// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- // Load MPB
+ /* Load MPB */
val = cpuid_eax(1);
printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
@@ -163,10 +159,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
post_code(0x39);
- if (!warm_reset_detect(0)) { // BSP is node 0
+ if (!warm_reset_detect(0)) { /* BSP is node 0 */
init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
} else {
- init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ init_fidvid_stage2(bsp_apicid, 0); /* BSP is node 0 */
}
post_code(0x3A);
@@ -193,8 +189,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x40);
-// die("Die Before MCT init.");
-
timestamp_add_now(TS_BEFORE_INITRAM);
printk(BIOS_DEBUG, "raminit_amdmct()\n");
raminit_amdmct(sysinfo);
@@ -205,23 +199,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
amdmct_cbmem_store_info(sysinfo);
-/*
- dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200);
- dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200);
-*/
-
-// ram_check(0x00200000, 0x00200000 + (640 * 1024));
-// ram_check(0x40200000, 0x40200000 + (640 * 1024));
-
-// die("After MCT init before CAR disabled.");
-
rs780_before_pci_init();
post_code(0x42);
- post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
- post_code(0x43); // Should never see this post code.
+ post_cache_as_ram(); /* BSP switch stack to ram, copy then execute LB. */
+ post_code(0x43); /* Should never see this post code. */
}
/**
More information about the coreboot-gerrit
mailing list