[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Disable HECI2 device reset on S3 resume

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 0910f4e76f05798e1a5d96cb4e7f202b290fb62e
Author: Andrey Petrov <andrey.petrov at intel.com>
Date:   Mon Oct 3 16:05:20 2016 -0700

    soc/intel/apollolake: Disable HECI2 device reset on S3 resume
    
    Converged Security Engine (CSE) has a secure variable storage feature.
    However, this storage is expected to be reset during S3 resume flow.
    Since coreboot does not use secure storage feature, disable HECI2 reset
    request. This saves appr. 130ms of resume time.
    
    BUG=chrome-os-partner:56941
    BRANCH=none
    TEST=powerd_dbus_suspend; resume; check time with cbmem -t. Note
    FspMemoryInit time is not significantly different from normal boot
    time case.
    
    Change-Id: I485a980369c6bd97c43b9e554d65ee89e84d8233
    Signed-off-by: Andrey Petrov <andrey.petrov at intel.com>
    Reviewed-on: https://review.coreboot.org/16870
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>


See https://review.coreboot.org/16870 for details.

-gerrit