[coreboot-gerrit] Patch merged into coreboot/master: google/gru: Add USB 2.0 PHY tuning for Kevin PHY0 and PHY1

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5b1bb3d980475a4af5b2feed078ec64437da2175
Author: William wu <wulf at rock-chips.com>
Date:   Thu Sep 29 15:18:41 2016 +0800

    google/gru: Add USB 2.0 PHY tuning for Kevin PHY0 and PHY1
    
    We found that Kevin board PHY0 and PHY1 eye-diagram margin
    is not enough to make compliance test pass, and the PHY0 USB
    SI is worse than PHY1, because of the higher PCB impedance.
    
    For PHY0, we can't improve the eye-diagram by SW PHY tuning,
    so we need to reduce the RBIAS resistance from 133 ohm to 115
    ohm, it can help to increase the eye-height.
    
    For PHY1, we can improve the eye-diagram by setting the max
    pre-emphasis level.
    
    And after the above change, the USB2 signal amplitude will
    become larger at the test point near to SOC USB2 PHY, in order
    to avoid mis-trigger the disconnect detection (650mV), we need
    to disable pre-emphasize in eop state.
    
    BRANCH=None
    BUG=chrome-os-partner:53863
    TEST=do USB 2.0 compliance test for Kevin C0 and C1 port.
    
    Change-Id: I95c0acd79623aeca9a0ae077b1dd3836d91fe561
    Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
    Original-Commit-Id: de3cdef128966d76e7d8e2ebd641763b911c3ad5
    Original-Change-Id: I00cb325b9938e4276cc77b5d6f5faa7023379608
    Original-Signed-off-by: William wu <wulf at rock-chips.com>
    Original-Reviewed-on: https://chromium-review.googlesource.com/390615
    Original-Commit-Ready: Julius Werner <jwerner at chromium.org>
    Original-Tested-by: Julius Werner <jwerner at chromium.org>
    Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
    Reviewed-on: https://review.coreboot.org/16911
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/16911 for details.

-gerrit