[coreboot-gerrit] Patch merged into coreboot/master: cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit aacd548c26f251583f1035d4ecc544198721f937
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Thu Oct 6 12:14:14 2016 +0200

    cpu/intel/model_6ex: Set msr bits for dynamic L2, C2E, C4E
    
    The datasheets "Intel® Core™ Duo Processor and Intel® Core™ Solo
    Processor on 65 nm Process" mentions cpu C-states substates which can
    either be attained by adding a substate hint to the MWAIT/P_LVLx request
    or automatically by setting some msr bits correctly.
    
    This just sets the same msr bits as model_6fx to enable
    dynamic L2 cache, C2E and C4E acpi cpu states.
    
    The result is that when limiting a thinkpad x60 with a yonah T2400
    cpu to the acpi cpu C2 state, the idle power usage drops from 18W to
    14W. When the lowest C-state is set to C4 the idle power usage seems
    to remain similar.
    
    Change-Id: I6c422656ace04659f32082a5944617eda6c79ec3
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
    Reviewed-on: https://review.coreboot.org/16901
    Tested-by: build bot (Jenkins)
    Reviewed-by: Martin Roth <martinroth at google.com>


See https://review.coreboot.org/16901 for details.

-gerrit