[coreboot-gerrit] Patch set updated for coreboot: nb/i945/gma.c: correct VSYNC end offset

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17015

-gerrit

commit e5559f8dc1a90528ec6788ee8285b15f8d7b72ef
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Thu Oct 13 14:12:45 2016 +0200

    nb/i945/gma.c: correct VSYNC end offset
    
    According to "G45: Volume 3: Display Register Intel ® 965G Express
    Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the
    VSYNC end should start at bit 16. This is also how Linux (at least 4.4)
    sets this register, which can be seen with intel-gpu-tools.
    
    TESTED on Lenovo thinkpad X60 (it does not change anything).
    
    Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/i945/gma.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index eeb377a..a4ad3bd 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -275,7 +275,7 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf,
 	write32(pmmio + VBLANK(1), ((vactive + bottom_border + vblank - 1) << 16)
 		| (vactive + bottom_border - 1));
 	write32(pmmio + VSYNC(1),
-		(vactive + bottom_border + vfront_porch + vsync - 1)
+		((vactive + bottom_border + vfront_porch + vsync - 1) << 16)
 		| (vactive + bottom_border + vfront_porch - 1));
 
 #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)