[coreboot-gerrit] Patch set updated for coreboot: soc/intel/skylake: Enable HECI BAR for ME communication
Subrata Banik (subrata.banik@intel.com)
gerrit at coreboot.org
Fri Oct 14 13:11:12 CEST 2016
Subrata Banik (subrata.banik at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17016
-gerrit
commit f0274a18c75d7aaeb13bd141632dc16dcbbac8ee
Author: Subrata Banik <subrata.banik at intel.com>
Date: Thu Oct 13 18:05:04 2016 +0530
soc/intel/skylake: Enable HECI BAR for ME communication
This patch programs and enables BAR for ME (bus:0/
device:0x16/function:0) device to have early ME communication.
BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message can able to perform platform
global reset during romstage.
Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
src/soc/intel/skylake/bootblock/pch.c | 23 +++++++++++++++++++++++
src/soc/intel/skylake/include/soc/iomap.h | 2 ++
2 files changed, 25 insertions(+)
diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
index 22ab109..57b5fed 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
+++ b/src/soc/intel/skylake/bootblock/pch.c
@@ -251,6 +251,27 @@ static void soc_config_rtc(void)
B_PCH_PCR_RTC_CONF_UCMOS_EN);
}
+static void enable_heci(void)
+{
+ device_t dev = PCH_DEV_ME;
+ u8 pcireg;
+
+ /* Assign Resources to HECI1 */
+ /* Clear BIT 1-2 of Command Register */
+ pcireg = pci_read_config8(dev, PCI_COMMAND);
+ pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+ pci_write_config8(dev, PCI_COMMAND, pcireg);
+
+ /* Program Temporary BAR for HECI1 */
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS);
+ pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
+
+ /* Enable Bus Master and MMIO Space */
+ pcireg = pci_read_config8(dev, PCI_COMMAND);
+ pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
+ pci_write_config8(dev, PCI_COMMAND, pcireg);
+}
+
void pch_early_init(void)
{
/*
@@ -281,4 +302,6 @@ void pch_early_init(void)
enable_smbus();
soc_config_rtc();
+
+ enable_heci();
}
diff --git a/src/soc/intel/skylake/include/soc/iomap.h b/src/soc/intel/skylake/include/soc/iomap.h
index feba302..e736d3b 100644
--- a/src/soc/intel/skylake/include/soc/iomap.h
+++ b/src/soc/intel/skylake/include/soc/iomap.h
@@ -56,6 +56,8 @@
#define GPIO_BASE_SIZE 0x10000
+#define HECI1_BASE_ADDRESS 0xfed1a000
+
/*
* I/O port address space
*/
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