[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: Set PL1 override to 12000mW

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17029

-gerrit

commit 8edc9a8bd71136cb8536a4ec4db6b1af8964dc5e
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date:   Fri Oct 14 15:29:33 2016 -0700

    mainboard/google/reef: Set PL1 override to 12000mW
    
    Reef is using APL SoC SKU's with 6W TDP max. We've done
    experiments and found the energy calculation is wrong with
    the current VR solutions. Experiments shows that SoC TDP max
    (6W) can be reached when RAPL PL1 is set to 12W. Therefore,
    we've inserted 12W override after reading the fused value (6W).
    So system can reach right performance with that firmware change.
    
    BUG=chrome-os-partner:56922
    TEST=webGL performance(fps) not impacted before and after S3.
    
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    
    Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0
---
 src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 989acd9..29962e4 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -48,6 +48,8 @@ chip soc/intel/apollolake
 
 	# Enable DPTF
 	register "dptf_enable" = "1"
+        # PL1 override 12000 mW
+        register "tdp_pl1_override_mw" = "12000"
 
 	# Enable Audio Clock and Power gating
 	register "hdaudio_clk_gate_enable" = "1"