[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: Configure PERST pin for reef DVT

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17030

-gerrit

commit 8b8ebbf9432ddad9806bc932f8a8f808af173d8e
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date:   Fri Oct 14 16:08:32 2016 -0700

    mainboard/google/reef: Configure PERST pin for reef DVT
    
    Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST
    during s0ix entry.
    
    
    BUG=chrome-os-partner:55877
    TEST=S0ix functional on DVT
    
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
    
    Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875
---
 src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 989acd9..5bb913e 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/apollolake
 	# GPIO for PERST_0
 	# If the Board has PERST_0 signal, assign the GPIO
 	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
-	register "prt0_gpio" = "GPIO_PRT0_UDEF"
+	register "prt0_gpio" = "GPIO_122"
 
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.