[coreboot-gerrit] Patch set updated for coreboot: nb/i945/raminit: Fix for 1067MHz fsb cpu's
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Sat Oct 15 23:57:24 CEST 2016
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17034
-gerrit
commit 44520d9c74d64800b9fe24c789d4085e83ce7d3e
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Sat Oct 15 23:29:18 2016 +0200
nb/i945/raminit: Fix for 1067MHz fsb cpu's
Previously the 945gc raminit only worked for 533MHz fsb cpu's.
This extends the tRD_Mclks table for other fsb speeds. The values are
taken from the vendor bios of Gigabyte ga-945gcm-s2l.
The result is that 1067MHz fsb cpus now boot without problems.
800MHz fsb cpus still don't get past romstage.
Change-Id: I13a6b97d2e580512155edf66c48405a153121957
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/northbridge/intel/i945/raminit.c | 30 ++++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index f1ad6c2..7e79b56 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1718,9 +1718,12 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
static const u8 drt0_table[] = {
/* CL 3, 4, 5 */
- 3, 4, 5, /* FSB533/400, DDR533/400 */
- 4, 5, 6, /* FSB667, DDR533/400 */
- 4, 5, 6, /* FSB667, DDR667 */
+ 3, 4, 5, /* FSB533, DDR667/533/400 */
+ 4, 5, 6, /* FSB667, DDR667/533/400 */
+ 5, 6, 7, /* FSB800, DDR400/533 */
+ 6, 7, 8, /* FSB800, DDR667 */
+ 5, 6, 7, /* FSB1066, DDR400 */
+ 7, 8, 9, /* FSB1066, DDR533/DDR667 */
};
static const u8 cas_table[] = {
@@ -1777,12 +1780,23 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
/* Program Write Auto Precharge to Activate */
off32 = 0;
- if (sysinfo->fsb_frequency == 667) { /* 667MHz FSB */
- off32 += 3;
- }
- if (sysinfo->memory_frequency == 667) {
- off32 += 3;
+ switch (sysinfo->fsb_frequency) {
+ case 533:
+ off32 = 0; break;
+ case 667:
+ off32 = 3; break;
+ case 800:
+ if (sysinfo->memory_frequency <= 533) {
+ off32 = 6; break;
+ }
+ off32 = 9; break;
+ case 1066:
+ if (sysinfo->memory_frequency == 400) {
+ off32 = 12; break;
+ }
+ off32 = 15; break;
}
+
off32 += sysinfo->cas - 3;
reg32 = drt0_table[off32];
temp_drt |= (reg32 << 11);
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