[coreboot-gerrit] Patch set updated for coreboot: kblrvp: Initial commit for intel/kblrvp3 mainboard
Naresh Solanki (naresh.solanki@intel.com)
gerrit at coreboot.org
Mon Oct 17 14:06:58 CEST 2016
Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17032
-gerrit
commit 3374a9f0a086123205552df082903ecf17227ea0
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date: Sat Oct 15 18:13:55 2016 +0530
kblrvp: Initial commit for intel/kblrvp3 mainboard
Initial commit to add support for Kabylake RVP3.
Using kunimitsu at commit 028200f as base.
Also,
* Update board name to kblrvp
* Remove fsp 1.1 specific code(As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.
Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
src/mainboard/intel/kblrvp/Kconfig | 64 ++++++
src/mainboard/intel/kblrvp/Kconfig.name | 2 +
src/mainboard/intel/kblrvp/Makefile.inc | 30 +++
src/mainboard/intel/kblrvp/acpi/dptf.asl | 129 +++++++++++
src/mainboard/intel/kblrvp/acpi/ec.asl | 27 +++
src/mainboard/intel/kblrvp/acpi/mainboard.asl | 44 ++++
src/mainboard/intel/kblrvp/acpi/superio.asl | 24 ++
src/mainboard/intel/kblrvp/acpi_tables.c | 15 ++
src/mainboard/intel/kblrvp/board_info.txt | 6 +
src/mainboard/intel/kblrvp/bootblock.c | 31 +++
src/mainboard/intel/kblrvp/chromeos.c | 94 ++++++++
src/mainboard/intel/kblrvp/chromeos.fmd | 38 ++++
src/mainboard/intel/kblrvp/cmos.layout | 133 +++++++++++
src/mainboard/intel/kblrvp/devicetree.cb | 316 ++++++++++++++++++++++++++
src/mainboard/intel/kblrvp/dsdt.asl | 55 +++++
src/mainboard/intel/kblrvp/ec.c | 46 ++++
src/mainboard/intel/kblrvp/ec.h | 59 +++++
src/mainboard/intel/kblrvp/fadt.c | 47 ++++
src/mainboard/intel/kblrvp/gpio.h | 243 ++++++++++++++++++++
src/mainboard/intel/kblrvp/mainboard.c | 109 +++++++++
src/mainboard/intel/kblrvp/ramstage.c | 24 ++
src/mainboard/intel/kblrvp/romstage.c | 42 ++++
src/mainboard/intel/kblrvp/smihandler.c | 71 ++++++
src/mainboard/intel/kblrvp/spd/Makefile.inc | 51 +++++
src/mainboard/intel/kblrvp/spd/empty.spd.hex | 16 ++
src/mainboard/intel/kblrvp/spd/rvp3.spd.hex | 17 ++
src/mainboard/intel/kblrvp/spd/spd.c | 93 ++++++++
src/mainboard/intel/kblrvp/spd/spd.h | 63 +++++
src/mainboard/intel/kblrvp/spd/spd_util.c | 118 ++++++++++
29 files changed, 2007 insertions(+)
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig
new file mode 100644
index 0000000..c3692a4
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/Kconfig
@@ -0,0 +1,64 @@
+if BOARD_INTEL_KBLRVP3
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select BOARD_ROMSIZE_KB_16384
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_SMI_HANDLER
+ select MAINBOARD_HAS_CHROMEOS
+ select MMCONF_SUPPORT
+ select MONOTONIC_TIMER_MSR
+ select SOC_INTEL_SKYLAKE
+ select MAINBOARD_USES_FSP2_0
+
+config CHROMEOS
+ select LID_SWITCH
+
+config DRIVERS_GENERIC_MAX98357A
+ default y
+
+config DRIVERS_I2C_GENERIC
+ default y
+
+config DRIVERS_I2C_NAU8825
+ default y
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAINBOARD_DIR
+ string
+ default "intel/kblrvp"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Kblrvp"
+
+config MAINBOARD_FAMILY
+ string
+ default "Intel_Kblrvp"
+
+config MAX_CPUS
+ int
+ default 8
+
+config TPM_PIRQ
+ hex
+ default 0x18 # GPP_E0_IRQ
+
+config INCLUDE_NHLT_BLOBS
+ bool "Include blobs for audio."
+ select NHLT_DMIC_2CH
+ select NHLT_DMIC_4CH
+ select NHLT_MAX98357
+ select NHLT_NAU88L25
+ select NHLT_SSM4567
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "KBLRVP TEST 8819"
+endif
diff --git a/src/mainboard/intel/kblrvp/Kconfig.name b/src/mainboard/intel/kblrvp/Kconfig.name
new file mode 100644
index 0000000..66ec552
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_KBLRVP3
+ bool "Kabylake LPDDR3 RVP3"
diff --git a/src/mainboard/intel/kblrvp/Makefile.inc b/src/mainboard/intel/kblrvp/Makefile.inc
new file mode 100644
index 0000000..de1da23
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/Makefile.inc
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += mainboard.c
+ramstage-y += ramstage.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/intel/kblrvp/acpi/dptf.asl b/src/mainboard/intel/kblrvp/acpi/dptf.asl
new file mode 100644
index 0000000..e011c97
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/acpi/dptf.asl
@@ -0,0 +1,129 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
+#define DPTF_ENABLE_CHARGER
+#define DPTF_ENABLE_FAN_CONTROL
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+#ifdef DPTF_ENABLE_FAN_CONTROL
+/* DFPS: Fan Performance States */
+Name (DFPS, Package () {
+ 0, // Revision
+ /*
+ * TODO : Need to update this Table after characterization.
+ * These are initial reference values.
+ */
+ /* Control, Trip Point, Speed, NoiseLevel, Power */
+ Package () {100, 0xFFFFFFFF, 4986, 220, 2200},
+ Package () {90, 0xFFFFFFFF, 4804, 180, 1800},
+ Package () {80, 0xFFFFFFFF, 4512, 145, 1450},
+ Package () {70, 0xFFFFFFFF, 4204, 115, 1150},
+ Package () {60, 0xFFFFFFFF, 3838, 90, 900},
+ Package () {50, 0xFFFFFFFF, 3402, 65, 650},
+ Package () {40, 0xFFFFFFFF, 2904, 45, 450},
+ Package () {30, 0xFFFFFFFF, 2337, 30, 300},
+ Package () {20, 0xFFFFFFFF, 1608, 15, 150},
+ Package () {10, 0xFFFFFFFF, 800, 10, 100},
+ Package () {0, 0xFFFFFFFF, 0, 0, 50}
+})
+
+Name (DART, Package () {
+ /* Fan effect on CPU */
+ 0, // Revision
+ Package () {
+ /*
+ * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6,
+ * AC7, AC8, AC9
+ */
+ \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0,
+ 0, 0, 0
+ }
+})
+#endif
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 8000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
+
+/* Include DPTF */
+#include <soc/intel/skylake/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/intel/kblrvp/acpi/ec.asl b/src/mainboard/intel/kblrvp/acpi/ec.asl
new file mode 100644
index 0000000..2203e2f
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/acpi/ec.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+#include "../gpio.h"
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/intel/kblrvp/acpi/mainboard.asl b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
new file mode 100644
index 0000000..1b8fe43
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/acpi/mainboard.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "../gpio.h"
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDS)
+ }
+
+ Name (_PRW, Package () { GPE_EC_WAKE, 5 })
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+}
+
+/*
+ * LPC Trusted Platform Module
+ */
+Scope (\_SB.PCI0.LPCB)
+{
+ #include <drivers/pc80/tpm/acpi/tpm.asl>
+}
diff --git a/src/mainboard/intel/kblrvp/acpi/superio.asl b/src/mainboard/intel/kblrvp/acpi/superio.asl
new file mode 100644
index 0000000..803d2e3
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/acpi/superio.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include "../ec.h"
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/intel/kblrvp/acpi_tables.c b/src/mainboard/intel/kblrvp/acpi_tables.c
new file mode 100644
index 0000000..526d637
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/acpi_tables.c
@@ -0,0 +1,15 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/intel/kblrvp/board_info.txt b/src/mainboard/intel/kblrvp/board_info.txt
new file mode 100644
index 0000000..2c48625
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Kblrvp Kabylake RVP3 LPDDR3
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/kblrvp/bootblock.c b/src/mainboard/intel/kblrvp/bootblock.c
new file mode 100644
index 0000000..627b4e8
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/bootblock.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+#include "gpio.h"
+
+static void early_config_gpio(void)
+{
+ /* This is a hack for FSP because it does things in MemoryInit()
+ * which it shouldn't do. We have to prepare certain gpios here
+ * because of the brokenness in FSP. */
+ gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
diff --git a/src/mainboard/intel/kblrvp/chromeos.c b/src/mainboard/intel/kblrvp/chromeos.c
new file mode 100644
index 0000000..a9704da
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/chromeos.c
@@ -0,0 +1,94 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <rules.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <string.h>
+#include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#include "gpio.h"
+#include "ec.h"
+
+#if ENV_RAMSTAGE
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH,
+ gpio_get(GPIO_EC_IN_RW), "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif /* ENV_RAMSTAGE */
+
+int get_lid_switch(void)
+{
+ /* Read lid switch state from the EC. */
+ return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
+}
+
+int get_developer_mode_switch(void)
+{
+ /* No physical developer mode switch. */
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+ /* Check for dedicated recovery switch first. */
+ if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY)
+ return 1;
+
+ /* Otherwise check if the EC has posted the keyboard recovery event. */
+ return !!(google_chromeec_get_events_b() &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int clear_recovery_mode_switch(void)
+{
+ /* Clear keyboard recovery event. */
+ return google_chromeec_clear_events_b(
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+}
+
+int get_write_protect_state(void)
+{
+ /* Read PCH_WP GPIO. */
+ return gpio_get(GPIO_PCH_WP);
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/kblrvp/chromeos.fmd b/src/mainboard/intel/kblrvp/chromeos.fmd
new file mode 100644
index 0000000..58b6127
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH at 0xff000000 0x1000000 {
+ SI_ALL at 0x0 0x200000 {
+ SI_DESC at 0x0 0x1000
+ SI_ME at 0x1000 0x1ff000
+ }
+ SI_BIOS at 0x200000 0xe00000 {
+ RW_SECTION_A at 0x0 0x3f0000 {
+ VBLOCK_A at 0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x3dffc0
+ RW_FWID_A at 0x3effc0 0x40
+ }
+ RW_SECTION_B at 0x3f0000 0x3f0000 {
+ VBLOCK_B at 0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x3dffc0
+ RW_FWID_B at 0x3effc0 0x40
+ }
+ RW_MRC_CACHE at 0x7e0000 0x10000
+ RW_ELOG at 0x7f0000 0x4000
+ RW_SHARED at 0x7f4000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x7f8000 0x2000
+ RW_NVRAM at 0x7fa000 0x6000
+ RW_LEGACY(CBFS)@0x800000 0x200000
+ WP_RO at 0xa00000 0x400000 {
+ RO_VPD at 0x0 0x4000
+ RO_UNUSED at 0x4000 0xc000
+ RO_SECTION at 0x10000 0x3f0000 {
+ FMAP at 0x0 0x800
+ RO_FRID at 0x800 0x40
+ RO_FRID_PAD at 0x840 0x7c0
+ GBB at 0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x300000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout
new file mode 100644
index 0000000..e6d8acc
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/cmos.layout
@@ -0,0 +1,133 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+## Copyright (C) 2016 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/intel/kblrvp/devicetree.cb b/src/mainboard/intel/kblrvp/devicetree.cb
new file mode 100644
index 0000000..8dded98
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/devicetree.cb
@@ -0,0 +1,316 @@
+chip soc/intel/skylake
+
+ # Enable deep Sx states
+ register "deep_s5_enable" = "1"
+ register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "gpe0_dw0" = "GPP_B"
+ register "gpe0_dw1" = "GPP_D"
+ register "gpe0_dw2" = "GPP_E"
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+
+ # Enable "Intel Speed Shift Technology"
+ register "speed_shift_enable" = "1"
+
+ # Enable DPTF
+ register "dptf_enable" = "1"
+
+ # FSP Configuration
+ register "EnableAzalia" = "1"
+ register "DspEnable" = "1"
+ register "IoBufferOwnership" = "3"
+ register "SmbusEnable" = "1"
+ register "ScsEmmcEnabled" = "1"
+ register "ScsEmmcHs400Enabled" = "1"
+ register "ScsSdCardEnabled" = "2"
+ register "InternalGfx" = "1"
+ register "SkipExtGfxScan" = "1"
+ register "Device4Enable" = "1"
+ register "HeciEnabled" = "0"
+ register "SaGv" = "3"
+ register "PmTimerDisabled" = "1"
+
+ register "pirqa_routing" = "PCH_IRQ11"
+ register "pirqb_routing" = "PCH_IRQ10"
+ register "pirqc_routing" = "PCH_IRQ11"
+ register "pirqd_routing" = "PCH_IRQ11"
+ register "pirqe_routing" = "PCH_IRQ11"
+ register "pirqf_routing" = "PCH_IRQ11"
+ register "pirqg_routing" = "PCH_IRQ11"
+ register "pirqh_routing" = "PCH_IRQ11"
+
+ # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch
+ # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s
+ register "PmConfigSlpS3MinAssert" = "0x02"
+
+ # SLP_S4 Minimum Assertion Width. Values 0: default, 1: 1s, 2: 2s, 3: 3s, 4: 4s
+ register "PmConfigSlpS4MinAssert" = "0x04"
+
+ # SLP_SUS Minimum Assertion Width. Values 0: 0ms, 1: 500ms, 2: 1s, 3: 4s
+ register "PmConfigSlpSusMinAssert" = "0x03"
+
+ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s
+ register "PmConfigSlpAMinAssert" = "0x03"
+
+ # Determines if enable Serial IRQ. Values 0: Disabled, 1: Enabled
+ register "SerialIrqConfigSirqEnable" = "0x01"
+
+ # VR Settings Configuration for 5 Domains
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ #| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
+ #| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
+ #| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
+ #| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
+ #| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
+ #| ImonSlope | 0 | 0 | 0 | 0 | 0 |
+ #| ImonOffset | 0 | 0 | 0 | 0 | 0 |
+ #| IccMax | 7A | 34A | 34A | 35A | 35A |
+ #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
+ #+----------------+-------+-------+-------------+-------------+-------+
+ register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x10, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x1C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_IA_CORE]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x88, \
+ .voltage_limit = 0x5F0 \
+ }"
+ register "domain_vr_config[VR_RING]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x88, \
+ .voltage_limit = 0x5F0, \
+ }"
+
+ register "domain_vr_config[VR_GT_UNSLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C ,\
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "domain_vr_config[VR_GT_SLICED]" = "{
+ .vr_config_enable = 1, \
+ .psi1threshold = 0x50, \
+ .psi2threshold = 0x14, \
+ .psi3threshold = 0x4, \
+ .psi3enable = 1, \
+ .psi4enable = 1, \
+ .imon_slope = 0x0, \
+ .imon_offset = 0x0, \
+ .icc_max = 0x8C, \
+ .voltage_limit = 0x5F0 \
+ }"
+
+ register "FspSkipMpInit" = "1"
+
+ # Enable Root port 1 and 5.
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpEnable[4]" = "1"
+ # Enable CLKREQ#
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ # RP 1 uses SRCCLKREQ1# while RP 5 uses SRCCLKREQ2#
+ register "PcieRpClkReqNumber[0]" = "1"
+ register "PcieRpClkReqNumber[4]" = "2"
+
+ register "usb2_ports[0]" = "USB2_PORT_TYPE_C" # Type-C Port 1
+ register "usb2_ports[1]" = "USB2_PORT_TYPE_C" # Type-C Port 2
+ register "usb2_ports[2]" = "USB2_PORT_MID" # Bluetooth
+ register "usb2_ports[4]" = "USB2_PORT_MID" # Type-A Port (card)
+ register "usb2_ports[6]" = "USB2_PORT_FLEX" # Camera
+ register "usb2_ports[8]" = "USB2_PORT_LONG" # Type-A Port (board)
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT" # Type-C Port 1
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT" # Type-C Port 2
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT" # Type-A Port (card)
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT" # Type-A Port (board)
+
+ register "i2c[4].voltage" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
+
+ # Must leave UART0 enabled or SD/eMMC will not work as PCI
+ register "SerialIoDevMode" = "{ \
+ [PchSerialIoIndexI2C0] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C1] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C2] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C3] = PchSerialIoDisabled, \
+ [PchSerialIoIndexI2C4] = PchSerialIoPci, \
+ [PchSerialIoIndexI2C5] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi0] = PchSerialIoDisabled, \
+ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart0] = PchSerialIoPci, \
+ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \
+ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \
+ }"
+
+ # PL2 override 25W
+ register "tdp_pl2_override" = "25"
+
+ # Send an extra VR mailbox command for the PS4 exit issue
+ register "SendVrMbxCmd" = "2"
+
+ # Enable/Disable VMX feature
+ register "VmxEnable" = "0"
+
+ # Use default SD card detect GPIO configuration
+ register "sdcard_cd_gpio_default" = "GPP_A7"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 14.0 on end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.2 on end # Thermal Subsystem
+ device pci 15.0 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0001""
+ register "desc" = ""ELAN Touchscreen""
+ register "irq" = "IRQ_EDGE_LOW(GPP_E7_IRQ)"
+ device i2c 10 on end
+ end
+ end # I2C #0
+ device pci 15.1 on
+ chip drivers/i2c/generic
+ register "hid" = ""ELAN0000""
+ register "desc" = ""ELAN Touchpad""
+ register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)"
+ register "wake" = "GPE0_DW0_05"
+ device i2c 15 on end
+ end
+ end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 on end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 17.0 off end # SATA
+ device pci 19.0 on end # UART #2
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 on
+ chip drivers/i2c/nau8825
+ register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)"
+ register "jkdet_enable" = "1"
+ register "jkdet_pull_enable" = "1"
+ register "jkdet_pull_up" = "1"
+ register "jkdet_polarity" = "1" # ActiveLow
+ register "vref_impedance" = "2" # 125kOhm
+ register "micbias_voltage" = "6" # 2.754
+ register "sar_threshold_num" = "4"
+ register "sar_threshold[0]" = "0x08"
+ register "sar_threshold[1]" = "0x12"
+ register "sar_threshold[2]" = "0x26"
+ register "sar_threshold[3]" = "0x73"
+ register "sar_hysteresis" = "0"
+ register "sar_voltage" = "6"
+ register "sar_compare_time" = "1" # 1us
+ register "sar_sampling_time" = "1" # 4us
+ register "short_key_debounce" = "3" # 30ms
+ register "jack_insert_debounce" = "7" # 512ms
+ register "jack_eject_debounce" = "0"
+ device i2c 1a on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""INT343B""
+ register "desc" = ""SSM4567 Left Speaker Amp""
+ register "uid" = "0"
+ register "device_present_gpio" = "GPP_E3"
+ device i2c 34 on end
+ end
+ chip drivers/i2c/generic
+ register "hid" = ""INT343B""
+ register "desc" = ""SSM4567 Right Speaker Amp""
+ register "uid" = "1"
+ register "device_present_gpio" = "GPP_E3"
+ device i2c 35 on end
+ end
+ end # I2C #4
+ device pci 1c.0 on
+ chip drivers/intel/wifi
+ register "wake" = "GPE0_DW0_16"
+ device pci 00.0 on end
+ end
+ end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 on end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1e.0 on end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1e.4 on end # eMMC
+ device pci 1e.5 off end # SDIO
+ device pci 1e.6 on end # SDCard
+ device pci 1f.0 on
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # LPC Interface
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 on end # Power Management Controller
+ device pci 1f.3 on
+ chip drivers/generic/max98357a
+ register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)"
+ register "device_present_gpio" = "GPP_E3"
+ register "device_present_gpio_invert" = "1"
+ device generic 0 on end
+ end
+ end # Intel HDA
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/intel/kblrvp/dsdt.asl b/src/mainboard/intel/kblrvp/dsdt.asl
new file mode 100644
index 0000000..ebbdeec
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/dsdt.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/skylake/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/skylake/acpi/globalnvs.asl>
+
+ // CPU
+ #include <soc/intel/skylake/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ }
+
+ // Dynamic Platform Thermal Framework
+ #include "acpi/dptf.asl"
+ }
+
+ // Chrome OS specific
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chipset specific sleep states
+ #include <soc/intel/skylake/acpi/sleepstates.asl>
+
+ // Mainboard specific
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/intel/kblrvp/ec.c b/src/mainboard/intel/kblrvp/ec.c
new file mode 100644
index 0000000..235ecab
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/ec.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ printk(BIOS_DEBUG, "mainboard: EC init\n");
+
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0)
+ ;
+
+ /* Restore SCI event mask */
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ }
+
+ /* Clear wake event mask */
+ google_chromeec_set_wake_mask(0);
+}
diff --git a/src/mainboard/intel/kblrvp/ec.h b/src/mainboard/intel/kblrvp/ec.h
new file mode 100644
index 0000000..ff5533c
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/ec.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+#endif
diff --git a/src/mainboard/intel/kblrvp/fadt.c b/src/mainboard/intel/kblrvp/fadt.c
new file mode 100644
index 0000000..49301e3
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/fadt.c
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 5;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum = acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h
new file mode 100644
index 0000000..0e03080
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/gpio.h
@@ -0,0 +1,243 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_GPIO_H
+#define MAINBOARD_GPIO_H
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_C6
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_C23
+
+/* Memory configuration board straps */
+#define GPIO_MEM_CONFIG_0 GPP_C12
+#define GPIO_MEM_CONFIG_1 GPP_C13
+#define GPIO_MEM_CONFIG_2 GPP_C14
+#define GPIO_MEM_CONFIG_3 GPP_C15
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_WLAN_WAKE GPE0_DW0_16
+
+/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
+#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
+
+/* Input device interrupt configuration */
+#define TOUCHPAD_INT_L GPP_B3_IRQ
+#define TOUCHSCREEN_INT_L GPP_E7_IRQ
+#define MIC_INT_L GPP_F10_IRQ
+
+/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
+#define EC_SCI_GPI GPE0_DW2_16
+#define EC_SMI_GPI GPP_E15
+
+/*
+ * GPP_E3 is AUDIO_DB_ID.
+ * It is a dual purpose GPIO, used for Audio Daughter
+ * Board Identification & to control the shutdown mode pin
+ * of the Maxim amp.
+ */
+#define AUDIO_DB_ID GPP_E3
+
+/* SD controller needs additional card detect GPIO to support RTD3 */
+#define GPIO_SD_CARD_DETECT GPP_A7
+
+#ifndef __ACPI__
+/* Pad configuration in ramstage. */
+static const struct pad_config gpio_table[] = {
+/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
+/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
+/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
+/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
+/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
+/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
+/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
+/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
+/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
+/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
+/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10),
+/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),
+/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
+/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
+/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
+/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
+/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),
+/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
+/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),
+/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),
+/* GYRO_INT */ PAD_CFG_NC(GPP_A22),
+/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
+/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
+/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
+/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
+/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
+/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),
+/* TOUCHPAD WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES),
+/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
+/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
+/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),
+/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
+/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
+/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
+/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
+/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
+/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),
+/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
+/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19),
+/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),
+/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),
+/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),
+/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
+/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
+/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
+/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
+/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),
+/* SML0DATA */ PAD_CFG_NC(GPP_C4),
+/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
+/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
+/* USB_CTL */ PAD_CFG_NC(GPP_C7),
+/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
+/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
+/* NFC_RST* */ PAD_CFG_NC(GPP_C10),
+/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
+/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
+/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
+/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP),
+/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP),
+/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1),
+/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1),
+/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
+/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
+/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
+/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
+/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
+/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0),
+/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),
+/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2),
+/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3),
+/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4),
+/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),
+/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
+/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
+/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
+/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),
+/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP),
+/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP),
+/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),
+/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13),
+/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
+/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15),
+/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16),
+/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
+/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
+/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
+/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21),
+/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22),
+/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
+/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST),
+/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
+/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),
+/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
+/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),
+/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
+/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
+/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
+/* SATALED# */ PAD_CFG_NC(GPP_E8),
+/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
+/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
+/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
+/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
+/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
+/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
+/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
+/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
+/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
+/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
+
+/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
+/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
+/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
+/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
+/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
+/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
+/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
+/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
+/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
+/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
+/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
+/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST),
+/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
+/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
+/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
+/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
+/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
+/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
+/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
+/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
+/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
+/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
+/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP),
+/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
+/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
+/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
+/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
+/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
+/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
+/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
+/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
+/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+/* GPD7 */ PAD_CFG_NC(GPD7),
+/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),
+/* PM_SLP_S5# */ PAD_CFG_NC(GPD10),
+/* LANPHYC */ PAD_CFG_NC(GPD11),
+};
+
+/* Early pad configuration in romstage. */
+static const struct pad_config early_gpio_table[] = {
+/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
+/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
+/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
+};
+
+#endif
+
+#endif
diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c
new file mode 100644
index 0000000..fe4fb3a
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/mainboard.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <gpio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include "ec.h"
+#include "gpio.h"
+
+static const char *oem_id_maxim = "INTEL";
+static const char *oem_table_id_maxim = "SCRDMAX";
+
+static void mainboard_init(device_t dev)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ mainboard_ec_init();
+}
+
+static uint8_t select_audio_codec(void)
+{
+ int audio_db_sel = gpio_get(AUDIO_DB_ID);
+
+ return audio_db_sel;
+}
+
+static unsigned long mainboard_write_acpi_tables(
+ device_t device, unsigned long current, acpi_rsdp_t *rsdp)
+{
+ uintptr_t start_addr;
+ uintptr_t end_addr;
+ struct nhlt *nhlt;
+ const char *oem_id = NULL;
+ const char *oem_table_id = NULL;
+
+ start_addr = current;
+
+ nhlt = nhlt_init();
+
+ if (nhlt == NULL)
+ return start_addr;
+
+ /* 2 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 2))
+ printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
+
+
+ /* 4 Channel DMIC array. */
+ if (nhlt_soc_add_dmic_array(nhlt, 4))
+ printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n");
+
+ if (select_audio_codec()) {
+ /* ADI Smart Amps for left and right. */
+ if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add ssm4567.\n");
+ } else {
+ /* MAXIM Smart Amps for left and right. */
+ if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0))
+ printk(BIOS_ERR, "Couldn't add max98357.\n");
+
+ oem_id = oem_id_maxim;
+ oem_table_id = oem_table_id_maxim;
+ }
+
+ /* NAU88l25 Headset codec. */
+ if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
+ printk(BIOS_ERR, "Couldn't add headset codec.\n");
+
+ end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr,
+ oem_id, oem_table_id);
+
+ if (end_addr != start_addr)
+ acpi_add_table(rsdp, (void *)start_addr);
+
+ return end_addr;
+}
+
+/*
+ * mainboard_enable is executed as first thing after
+ * enumerate_buses().
+ */
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/kblrvp/ramstage.c b/src/mainboard/intel/kblrvp/ramstage.c
new file mode 100644
index 0000000..ed37681
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/ramstage.c
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/ramstage.h>
+#include "gpio.h"
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ /* Configure pads prior to SiliconInit() in case there's any
+ * dependencies during hardware initialization. */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c
new file mode 100644
index 0000000..d4fd113
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/romstage.c
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <gpio.h>
+#include "gpio.h"
+#include <soc/romstage.h>
+#include <soc/gpio.h>
+#include "spd/spd.h"
+#include <string.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg;
+ mem_cfg = &mupd->FspmConfig;
+
+ mainboard_fill_dq_map_data(&mem_cfg->DqByteMapCh0);
+ mainboard_fill_dqs_map_data(&mem_cfg->DqsMapCpu2DramCh0);
+ mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor);
+ mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget);
+
+ mem_cfg->DqPinsInterleaved = 0;
+ mem_cfg->MemorySpdPtr00 = mainboard_get_spd_data();
+ if (mainboard_has_dual_channel_mem())
+ mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
+ mem_cfg->MemorySpdDataLen = SPD_LEN;
+}
diff --git a/src/mainboard/intel/kblrvp/smihandler.c b/src/mainboard/intel/kblrvp/smihandler.c
new file mode 100644
index 0000000..81aaf23
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/smihandler.c
@@ -0,0 +1,71 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+#include <ec/google/chromeec/smm.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
+#include "ec.h"
+#include "gpio.h"
+
+int mainboard_io_trap_handler(int smif)
+{
+ switch (smif) {
+ case 0x99:
+ printk(BIOS_DEBUG, "Sample\n");
+ smm_get_gnvs()->smif = 0;
+ break;
+ default:
+ return 0;
+ }
+
+ /* On success, the IO Trap Handler returns 0
+ * On failure, the IO Trap Handler returns a value != 0
+ *
+ * For now, we force the return value to 0 and log all traps to
+ * see what's going on.
+ */
+ return 1;
+}
+
+void mainboard_smi_gpi_handler(const struct gpi_status *sts)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (gpi_status_get(sts, EC_SMI_GPI))
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS,
+ MAINBOARD_EC_SMI_EVENTS);
+ return 0;
+}
diff --git a/src/mainboard/intel/kblrvp/spd/Makefile.inc b/src/mainboard/intel/kblrvp/spd/Makefile.inc
new file mode 100644
index 0000000..0a20c0d
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/Makefile.inc
@@ -0,0 +1,51 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2015 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = rvp3 # 0b0000 Dual Channel 4GB
+SPD_SOURCES += empty # 0b0001 Single Channel 2GB
+SPD_SOURCES += empty # 0b0010 Dual Channel 4GB
+SPD_SOURCES += empty # 0b0011 Dual Channel 8GB
+SPD_SOURCES += empty # 0b0100 Single Channel 4GB
+SPD_SOURCES += empty # 0b0101 Single Channel 4GB SPD FILE NOT HERE YET
+SPD_SOURCES += empty # 0b0110 Dual Channel 4GB SPD FILE NOT HERE YET
+SPD_SOURCES += empty # 0b0111 Dual Channel 8GB SPD FILE NOT HERE YET
+SPD_SOURCES += empty # 0b1000
+SPD_SOURCES += empty # 0b1001
+SPD_SOURCES += empty # 0b1010
+SPD_SOURCES += empty # 0b1011
+SPD_SOURCES += empty # 0b1100
+SPD_SOURCES += empty # 0b1101
+SPD_SOURCES += empty # 0b1110
+SPD_SOURCES += empty # 0b1111
+
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/intel/kblrvp/spd/empty.spd.hex b/src/mainboard/intel/kblrvp/spd/empty.spd.hex
new file mode 100644
index 0000000..9ec39f1
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/empty.spd.hex
@@ -0,0 +1,16 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
new file mode 100644
index 0000000..1268a71
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
@@ -0,0 +1,17 @@
+24 20 F1 0E 14 11 95 00 00 00 00 03 0B 23 00 00
+00 00 0A FF 54 00 00 00 78 00 90 A8 90 10 04 E0
+01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+
diff --git a/src/mainboard/intel/kblrvp/spd/spd.c b/src/mainboard/intel/kblrvp/spd/spd.c
new file mode 100644
index 0000000..fe30621
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/spd.c
@@ -0,0 +1,93 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/pei_data.h>
+#include <soc/romstage.h>
+#include <string.h>
+
+#include "spd.h"
+
+static void mainboard_print_spd_info(uint8_t spd[])
+{
+ const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 };
+ const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 };
+ const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 };
+ const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 };
+ const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 };
+ const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 };
+ char spd_name[SPD_PART_LEN+1] = { 0 };
+
+ int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7];
+ int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256;
+ int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7];
+ int cols = spd_cols[spd[SPD_ADDRESSING] & 7];
+ int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7];
+ int devw = spd_devw[spd[SPD_ORGANIZATION] & 7];
+ int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7];
+
+ /* Module type */
+ printk(BIOS_INFO, "SPD: module type is ");
+ switch (spd[SPD_DRAM_TYPE]) {
+ case SPD_DRAM_DDR3:
+ printk(BIOS_INFO, "DDR3\n");
+ break;
+ case SPD_DRAM_LPDDR3:
+ printk(BIOS_INFO, "LPDDR3\n");
+ break;
+ default:
+ printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]);
+ break;
+ }
+
+ /* Module Part Number */
+ memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN);
+ spd_name[SPD_PART_LEN] = 0;
+ printk(BIOS_INFO, "SPD: module part is %s\n", spd_name);
+
+ printk(BIOS_INFO,
+ "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n",
+ banks, ranks, rows, cols, capmb);
+ printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n",
+ devw, busw);
+
+ if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
+ /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
+ printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
+ capmb / 8 * busw / devw * ranks);
+ }
+}
+
+/* Copy SPD data for on-board memory */
+void mainboard_fill_spd_data(struct pei_data *pei_data)
+{
+ uintptr_t spd_data;
+ spd_data = mainboard_get_spd_data();
+
+ memcpy(pei_data->spd_data[0][0], (void *)spd_data, SPD_LEN);
+
+ if (mainboard_has_dual_channel_mem())
+ memcpy(pei_data->spd_data[1][0], (void *)spd_data, SPD_LEN);
+
+ /* Make sure a valid SPD was found */
+ if (pei_data->spd_data[0][0][0] == 0)
+ die("Invalid SPD data.");
+
+ mainboard_print_spd_info(pei_data->spd_data[0][0]);
+}
diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h
new file mode 100644
index 0000000..e04d13c
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/spd.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+
+#include <gpio.h>
+#include "../gpio.h"
+
+#define MAINBOARD_SPD_H
+
+#define SPD_LEN 256
+
+#define SPD_DRAM_TYPE 2
+#define SPD_DRAM_DDR3 0x0b
+#define SPD_DRAM_LPDDR3 0xf1
+#define SPD_DENSITY_BANKS 4
+#define SPD_ADDRESSING 5
+#define SPD_ORGANIZATION 7
+#define SPD_BUS_DEV_WIDTH 8
+#define SPD_PART_OFF 128
+#define SPD_PART_LEN 18
+#define SPD_MANU_OFF 148
+
+#define HYNIX_SINGLE_CHAN 0x1
+#define SAMSUNG_SINGLE_CHAN 0x4
+#define MIC_SINGLE_CHAN 0x5
+
+/* PCH_MEM_CFG[3:0] */
+#define MAX_MEMORY_CONFIG 0x10
+#define RCOMP_TARGET_PARAMS 0x5
+#define K4E6E304EE_MEM_ID 0x3
+
+static inline int get_spd_index(void)
+{
+ /* PCH_MEM_CFG[3:0] */
+ gpio_t spd_gpios[] = {
+ GPIO_MEM_CONFIG_0,
+ GPIO_MEM_CONFIG_1,
+ GPIO_MEM_CONFIG_2,
+ GPIO_MEM_CONFIG_3,
+ };
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
+void mainboard_fill_dq_map_data(void *dq_map_ptr);
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr);
+uintptr_t mainboard_get_spd_data(void);
+int mainboard_has_dual_channel_mem(void);
+#endif
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
new file mode 100644
index 0000000..fc0581c
--- /dev/null
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -0,0 +1,118 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <arch/byteorder.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <stdint.h>
+#include <string.h>
+#include <soc/pei_data.h>
+#include <soc/pei_wrapper.h>
+#include "boardid.h"
+#include "spd.h"
+
+void mainboard_fill_dq_map_data(void *dq_map_ptr)
+{
+ /* DQ byte map */
+ const u8 dq_map[2][12] = {
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
+ { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
+ 0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+ memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
+{
+ /* DQS CPU<>DRAM map */
+ const u8 dqs_map[2][8] = {
+ { 0, 1, 3, 2, 6, 5, 4, 7 },
+ { 2, 3, 0, 1, 6, 7, 4, 5 } };
+ memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
+}
+
+void mainboard_fill_rcomp_res_data(void *rcomp_ptr)
+{
+ /* Rcomp resistor */
+ const u16 RcompResistor[3] = { 200, 81, 162 };
+ memcpy(rcomp_ptr, RcompResistor,
+ sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr)
+{
+ int mem_cfg_id;
+
+ mem_cfg_id = get_spd_index();
+ /* Rcomp target */
+ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = {
+ 100, 40, 40, 23, 40 };
+
+ /* Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF */
+ static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = {
+ 100, 40, 40, 21, 40 };
+
+
+ if (mem_cfg_id == K4E6E304EE_MEM_ID) {
+ memcpy(rcomp_strength_ptr, StrengthendRcompTarget,
+ sizeof(StrengthendRcompTarget));
+ } else {
+ memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget));
+ }
+
+}
+
+uintptr_t mainboard_get_spd_data(void)
+{
+ char *spd_file;
+ int spd_index, spd_span;
+ size_t spd_file_len;
+
+ spd_index = get_spd_index();
+ printk(BIOS_INFO, "SPD index %d\n", spd_index);
+
+ /* Load SPD data from CBFS */
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_file_len);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ /* make sure we have at least one SPD in the file. */
+ if (spd_file_len < SPD_LEN)
+ die("Missing SPD data.");
+
+ /* Make sure we did not overrun the buffer */
+ if (spd_file_len < ((spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spd_index = 0;
+ }
+
+ spd_span = spd_index * SPD_LEN;
+ return (uintptr_t)(spd_file + spd_span);
+}
+
+int mainboard_has_dual_channel_mem(void)
+{
+ int spd_index;
+
+ spd_index = get_spd_index();
+
+ if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN
+ && spd_index != MIC_SINGLE_CHAN) {
+ printk(BIOS_INFO,
+ "Dual channel SPD detected writing second channel\n");
+ return 1;
+ }
+ return 0;
+}
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