[coreboot-gerrit] Patch set updated for coreboot: RISCV: hacks for nexys4 and lowrisc.
Ronald G. Minnich (rminnich@gmail.com)
gerrit at coreboot.org
Mon Oct 17 16:25:37 CEST 2016
Ronald G. Minnich (rminnich at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16957
-gerrit
commit 3521ba813b00790934cf2724867e4c09ec463120
Author: Ronald G. Minnich <rminnich at gmail.com>
Date: Sun Oct 9 11:07:21 2016 -0700
RISCV: hacks for nexys4 and lowrisc.
Still not quite right.
Change-Id: Ieb56d964f2912c7a05c612611d259fd4e056a665
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
---
src/arch/riscv/trap_handler.c | 1 +
src/arch/riscv/virtual_memory.c | 8 ++++++--
src/mainboard/lowrisc/nexys4ddr/Kconfig | 15 +--------------
src/mainboard/lowrisc/nexys4ddr/bootblock.c | 30 -----------------------------
src/mainboard/lowrisc/nexys4ddr/mainboard.c | 3 ---
src/mainboard/lowrisc/nexys4ddr/rom_media.c | 3 +--
src/mainboard/lowrisc/nexys4ddr/uart.c | 4 +++-
src/mainboard/lowrisc/nexys4ddr/util.c | 11 -----------
8 files changed, 12 insertions(+), 63 deletions(-)
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index 59aa221..ba7c555 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -163,6 +163,7 @@ void trap_handler(trapframe *tf) {
break;
}
+ //print_page_table();
die("Can't recover from trap. Halting.\n");
}
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 7fb1a8e..6865e39 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -94,7 +94,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level)
/* Print the page table structures to the console */
void print_page_table(void) {
- print_page_table_at(root_page_table, 0, 0);
+ print_page_table_at((void *)(read_csr(sptbr)<<12), 0, 0);
}
void flush_tlb(void)
@@ -121,7 +121,7 @@ pte_t pte_create(uintptr_t ppn, int prot, int user)
pte |= PTE_X;
if (user)
pte |= PTE_U;
- return pte;
+ return pte | 0x1f;
}
void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) {
@@ -235,6 +235,10 @@ void mstatus_init(void)
*/
/* Enable all user/supervisor-mode counters */
+ /* We'll turn these on once lowrisc gets their bitstream up to
+ * 1.9. Right now there's no agreement on the values for these
+ * architectural registers.
+ */
//write_csr(mscounteren, 0b111);
//write_csr(mucounteren, 0b111);
}
diff --git a/src/mainboard/lowrisc/nexys4ddr/Kconfig b/src/mainboard/lowrisc/nexys4ddr/Kconfig
index 8283ecf..f0a3637 100644
--- a/src/mainboard/lowrisc/nexys4ddr/Kconfig
+++ b/src/mainboard/lowrisc/nexys4ddr/Kconfig
@@ -1,7 +1,7 @@
##
## This file is part of the coreboot project.
##
-## Copyright (C) 2014 Google Inc.
+## Copyright (C) 2016 Google Inc.
##
## This software is licensed under the terms of the GNU General Public
## License version 2, as published by the Free Software Foundation, and
@@ -12,16 +12,12 @@
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
-# To execute, do:
-# qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
-
if BOARD_LOWRISC_NEXYS4DDR
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select SOC_LOWRISC_LOWRISC
select BOARD_ROMSIZE_KB_4096
- select ARCH_BOOTBLOCK_RISCV
select DRIVERS_UART_8250MEM
select BOOT_DEVICE_NOT_SPI_FLASH
select UART_OVERRIDE_REFCLK
@@ -39,13 +35,4 @@ config MAX_CPUS
int
default 1
-config MAINBOARD_VENDOR
- string
- default "lowrisc"
-
-config DRAM_SIZE_MB
- int
- default 32768
-
-
endif # BOARD_LOWRISC_NEXYS4DDR
diff --git a/src/mainboard/lowrisc/nexys4ddr/bootblock.c b/src/mainboard/lowrisc/nexys4ddr/bootblock.c
deleted file mode 100644
index 40a7de1..0000000
--- a/src/mainboard/lowrisc/nexys4ddr/bootblock.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/exception.h>
-#include <bootblock_common.h>
-#include <console/console.h>
-#include <program_loading.h>
-
-// the qemu part of all this is very, very non-hardware like.
-// so it gets its own bootblock.
-void main(void)
-{
- if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
- console_init();
- exception_init();
- }
- run_romstage();
-}
diff --git a/src/mainboard/lowrisc/nexys4ddr/mainboard.c b/src/mainboard/lowrisc/nexys4ddr/mainboard.c
index 5687341..3b883ce 100644
--- a/src/mainboard/lowrisc/nexys4ddr/mainboard.c
+++ b/src/mainboard/lowrisc/nexys4ddr/mainboard.c
@@ -20,9 +20,6 @@
static void mainboard_enable(device_t dev)
{
/*
- * Size of the emulated system RAM. On hardware, this would be external
- * DDR memory.
- *
* TODO: Get this size from the hardware-supplied configuration string.
*/
const size_t ram_size = 1*GiB;
diff --git a/src/mainboard/lowrisc/nexys4ddr/rom_media.c b/src/mainboard/lowrisc/nexys4ddr/rom_media.c
index 10952a3..26a3b02 100644
--- a/src/mainboard/lowrisc/nexys4ddr/rom_media.c
+++ b/src/mainboard/lowrisc/nexys4ddr/rom_media.c
@@ -18,8 +18,7 @@
/*
* 0x80000000 is this start of RAM. We currently need to load coreboot.rom into
- * RAM on SPIKE, because SPIKE doesn't support loading custom code into the
- * boot ROM.
+ * RAM. The actual "rom" code on the FPGAs is in a block ram.
*/
static const struct mem_region_device boot_dev =
MEM_REGION_DEV_RO_INIT(0x80000000, CONFIG_ROM_SIZE);
diff --git a/src/mainboard/lowrisc/nexys4ddr/uart.c b/src/mainboard/lowrisc/nexys4ddr/uart.c
index 9551b20..128c736 100644
--- a/src/mainboard/lowrisc/nexys4ddr/uart.c
+++ b/src/mainboard/lowrisc/nexys4ddr/uart.c
@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
- * Copyright 2014 Google Inc.
+ * Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -24,6 +24,8 @@ uintptr_t uart_platform_base(int idx)
return (uintptr_t) 0x42000000;
}
+/* these are currently not quite right but they are here for reference
+ * and will be fixed soon. */
// divisor = clk_freq / (16 * Baud)
unsigned int uart_input_clock_divider(void)
{
diff --git a/src/mainboard/lowrisc/nexys4ddr/util.c b/src/mainboard/lowrisc/nexys4ddr/util.c
index 23aa117..32cdb6d 100644
--- a/src/mainboard/lowrisc/nexys4ddr/util.c
+++ b/src/mainboard/lowrisc/nexys4ddr/util.c
@@ -35,17 +35,6 @@
#include <string.h>
#include <vm.h>
-uintptr_t translate_address(uintptr_t vAddr)
-{
- // TODO: implement the page table translation algorithm
- //uintptr_t pageTableRoot = read_csr(sptbr);
- uintptr_t physAddrMask = 0xfffffff;
- uintptr_t translationResult = vAddr & physAddrMask;
- printk(BIOS_DEBUG, "Translated virtual address 0x%llx to physical address 0x%llx\n",
- vAddr, translationResult);
- return translationResult;
-}
-
uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info)
{
if (id == 0) {
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