[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/leafhill: add LeafHill CRB mainboard directory
Brenton Dong (brenton.m.dong@intel.com)
gerrit at coreboot.org
Thu Oct 20 01:16:14 CEST 2016
Brenton Dong (brenton.m.dong at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17065
-gerrit
commit ad39b8432712ae4234b5805e821d46edbef4f4a7
Author: brenton <brenton.m.dong at intel.com>
Date: Wed Oct 19 14:40:39 2016 -0700
mainboard/intel/leafhill: add LeafHill CRB mainboard directory
LeafHill CRB is an Intel Customer Reference Board with ApolloLake
silicon and LPDDR4 Down
Verified on Intel LeafHill CRB and confirmed to boot
Change-Id: Ieeed6a7e5e9b6f02e4dd7e15cbcb58894c3c4eac
Signed-off-by: brenton <brenton.m.dong at intel.com>
---
src/mainboard/intel/leafhill/Kconfig | 45 ++++++++++
src/mainboard/intel/leafhill/Kconfig.name | 3 +
src/mainboard/intel/leafhill/Makefile.inc | 64 ++++++++++++++
src/mainboard/intel/leafhill/acpi_tables.c | 14 +++
src/mainboard/intel/leafhill/board.h | 36 ++++++++
src/mainboard/intel/leafhill/board_info.txt | 6 ++
src/mainboard/intel/leafhill/brd_gpio.h | 65 ++++++++++++++
src/mainboard/intel/leafhill/devicetree.cb | 56 ++++++++++++
src/mainboard/intel/leafhill/dsdt.asl | 37 ++++++++
src/mainboard/intel/leafhill/ibb_fmap.fmd | 6 ++
src/mainboard/intel/leafhill/obb_fmap.fmd | 6 ++
src/mainboard/intel/leafhill/romstage.c | 128 ++++++++++++++++++++++++++++
12 files changed, 466 insertions(+)
diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig
new file mode 100644
index 0000000..462e458
--- /dev/null
+++ b/src/mainboard/intel/leafhill/Kconfig
@@ -0,0 +1,45 @@
+if BOARD_INTEL_LEAFHILL
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_APOLLOLAKE
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+
+config MAINBOARD_DIR
+ string
+ default intel/leafhill
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "LeafHill"
+
+config MAINBOARD_VENDOR
+ string
+ default "Intel"
+
+config IFD_BIOS_END
+ hex
+ default 0x6FF000
+
+config IFD_BIOS_START
+ hex
+ default 0x1000
+
+config IBBL_ROM_SIZE
+ hex
+ default 0x10000
+
+config IBBM_ROM_SIZE
+ hex
+ default 0x62000
+
+config OBB_ROM_SIZE
+ hex
+ default 0x100000
+
+config OBB_ROM_BASE
+ hex
+ default 0x200000
+
+endif
diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name
new file mode 100644
index 0000000..72664cd
--- /dev/null
+++ b/src/mainboard/intel/leafhill/Kconfig.name
@@ -0,0 +1,3 @@
+config BOARD_INTEL_LEAFHILL
+ bool "LeafHill"
+
diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc
new file mode 100644
index 0000000..271b20a
--- /dev/null
+++ b/src/mainboard/intel/leafhill/Makefile.inc
@@ -0,0 +1,64 @@
+#Nothing here yet
+
+MAINBOARD_PATH := $(src)/mainboard/$(call strip_quotes,$(CONFIG_MAINBOARD_DIR))
+IBB_FLASHMAP := $(MAINBOARD_PATH)/ibb_fmap.fmd
+
+IBBL_FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_IBBL_ROM_SIZE))
+IBBL_FMAP_ROM_SIZE := $(CONFIG_IBBL_ROM_SIZE)
+IBBL_FMAP_BIOS_BASE := 0
+IBBL_FMAP_BIOS_SIZE := $(IBBL_FMAP_ROM_SIZE)
+IBBL_FMAP_FMAP_BASE := 0
+IBBL_FMAP_FMAP_SIZE := 0x100
+IBBL_FMAP_CBFS_BASE := $(IBBL_FMAP_FMAP_SIZE)
+IBBL_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBL_FMAP_BIOS_SIZE) $(IBBL_FMAP_FMAP_SIZE))
+
+$(obj)/ibbl_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc
+ sed -e "s,##ROM_BASE##,$(IBBL_FMAP_ROM_ADDR)," \
+ -e "s,##ROM_SIZE##,$(IBBL_FMAP_ROM_SIZE)," \
+ -e "s,##BIOS_BASE##,$(IBBL_FMAP_BIOS_BASE)," \
+ -e "s,##BIOS_SIZE##,$(IBBL_FMAP_BIOS_SIZE)," \
+ -e "s,##FMAP_BASE##,$(IBBL_FMAP_FMAP_BASE)," \
+ -e "s,##FMAP_SIZE##,$(IBBL_FMAP_FMAP_SIZE)," \
+ -e "s,##CBFS_BASE##,$(IBBL_FMAP_CBFS_BASE)," \
+ -e "s,##CBFS_SIZE##,$(IBBL_FMAP_CBFS_SIZE)," \
+ $(IBB_FLASHMAP) > $@.tmp
+ mv $@.tmp $@
+
+# generated at the same time as ibbl_fmap.fmap
+$(obj)/ibbl_fmap_config.h: $(obj)/ibbl_fmap.fmap
+$(obj)/ibbl_fmap.desc: $(obj)/ibbl_fmap.fmap
+$(obj)/ibbl_fmap.fmap: $(obj)/ibbl_fmap.fmd $(FMAPTOOL)
+ echo " FMAP $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h $< $@"
+ $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h -R $(obj)/ibbl_fmap.desc $< $@
+
+
+IBBM_FMAP_CAR_TOP := $(call int-add, $(CONFIG_DCACHE_RAM_BASE) $(CONFIG_DCACHE_RAM_SIZE))
+IBBM_FMAP_ROM_ADDR := $(call int-subtract, $(IBBM_FMAP_CAR_TOP) $(CONFIG_IBBM_ROM_SIZE))
+IBBM_FMAP_ROM_SIZE := $(CONFIG_IBBM_ROM_SIZE)
+IBBM_FMAP_BIOS_BASE := 0
+IBBM_FMAP_BIOS_SIZE := $(IBBM_FMAP_ROM_SIZE)
+IBBM_FMAP_FMAP_BASE := 0
+IBBM_FMAP_FMAP_SIZE := 0x100
+IBBM_FMAP_CBFS_BASE := $(IBBM_FMAP_FMAP_SIZE)
+IBBM_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBM_FMAP_BIOS_SIZE) $(IBBM_FMAP_FMAP_SIZE))
+
+$(obj)/ibbm_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc
+ sed -e "s,##ROM_BASE##,$(IBBM_FMAP_ROM_ADDR)," \
+ -e "s,##ROM_SIZE##,$(IBBM_FMAP_ROM_SIZE)," \
+ -e "s,##BIOS_BASE##,$(IBBM_FMAP_BIOS_BASE)," \
+ -e "s,##BIOS_SIZE##,$(IBBM_FMAP_BIOS_SIZE)," \
+ -e "s,##FMAP_BASE##,$(IBBM_FMAP_FMAP_BASE)," \
+ -e "s,##FMAP_SIZE##,$(IBBM_FMAP_FMAP_SIZE)," \
+ -e "s,##CBFS_BASE##,$(IBBM_FMAP_CBFS_BASE)," \
+ -e "s,##CBFS_SIZE##,$(IBBM_FMAP_CBFS_SIZE)," \
+ $(IBB_FLASHMAP) > $@.tmp
+ mv $@.tmp $@
+
+# generated at the same time as ibbm_fmap.fmap
+$(obj)/ibbm_fmap_config.h: $(obj)/ibbm_fmap.fmap
+$(obj)/ibbm_fmap.desc: $(obj)/ibbm_fmap.fmap
+$(obj)/ibbm_fmap.fmap: $(obj)/ibbm_fmap.fmd $(FMAPTOOL)
+ echo " FMAP $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h $< $@"
+ $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h -R $(obj)/ibbm_fmap.desc $< $@
+
+# brenton: changed this to headerromstage-y += brd_gpio.c
diff --git a/src/mainboard/intel/leafhill/acpi_tables.c b/src/mainboard/intel/leafhill/acpi_tables.c
new file mode 100644
index 0000000..8d4d1cf
--- /dev/null
+++ b/src/mainboard/intel/leafhill/acpi_tables.c
@@ -0,0 +1,14 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Blank file required by build system assumptions of this file being present.
+ */
diff --git a/src/mainboard/intel/leafhill/board.h b/src/mainboard/intel/leafhill/board.h
new file mode 100644
index 0000000..90e2a10
--- /dev/null
+++ b/src/mainboard/intel/leafhill/board.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_BOARD_H_
+#define _SOC_BOARD_H_
+
+typedef struct {
+ uint32_t VendorDeviceId; //Codec Vendor/Device ID
+ uint8_t RevisionId; //Coden Revision ID. 0xFF matches any rev
+ uint8_t SdiNo; //SDI number, 0xFF matches any SDI.
+ uint16_t DataDwords; //Number of data DWORDs following header
+ uint8_t FrontPanelSupport;
+ uint8_t Padding[3];
+} BL_HDA_VERB_TABLE_HEADER;
+
+typedef struct {
+ BL_HDA_VERB_TABLE_HEADER VerbTableHeader;
+ uint32_t VerbTableData[];
+} BL_HDAUDIO_VERB_TABLE;
+
+void config_board_gpio(void);
+
+
+#endif
diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt
new file mode 100644
index 0000000..eb95944
--- /dev/null
+++ b/src/mainboard/intel/leafhill/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Apollolake RVP Reference Board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h
new file mode 100644
index 0000000..3cd47a7
--- /dev/null
+++ b/src/mainboard/intel/leafhill/brd_gpio.h
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <soc/mmio.h>
+#include <soc/gpio.h>
+#include "board.h"
+
+#if ENV_ROMSTAGE
+
+static const struct pad_config gpio_table[] = {
+ PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */
+ PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */
+ PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */
+ PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */
+
+ PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
+
+ /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */
+ PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1),
+ /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */
+ PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1),
+
+ PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */
+ PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */
+ PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */
+ PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */
+ PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */
+
+ PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */
+
+ PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1),
+ PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1),
+};
+
+#endif
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
new file mode 100644
index 0000000..746aaf3
--- /dev/null
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -0,0 +1,56 @@
+chip soc/intel/apollolake
+
+ register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2
+ register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot
+ register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1
+ register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
+ register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # - Host Bridge
+ device pci 00.1 on end # - DPTF
+ device pci 00.2 on end # - NPK
+ device pci 02.0 on end # - Gen
+ device pci 03.0 on end # - Iunit
+ device pci 0d.0 on end # - P2SB
+ device pci 0d.1 on end # - PMC
+ device pci 0d.2 on end # - SPI
+ device pci 0d.3 on end # - Shared SRAM
+ device pci 0e.0 on end # - Audio
+ device pci 11.0 on end # - ISH
+ device pci 12.0 on end # - SATA
+ device pci 13.0 on end # - PCIe-A 0
+ device pci 13.2 on end # - Onboard Lan
+ device pci 13.3 on end # - PCIe-A 3
+ device pci 14.0 on end # - PCIe-B 0
+ device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT)
+ device pci 15.0 on end # - XHCI
+ device pci 15.1 on end # - XDCI
+ device pci 16.0 on end # - I2C 0
+ device pci 16.1 on end # - I2C 1
+ device pci 16.2 on end # - I2C 2
+ device pci 16.3 on end # - I2C 3
+ device pci 17.0 on end # - I2C 4
+ device pci 17.1 on end # - I2C 5
+ device pci 17.2 on end # - I2C 6
+ device pci 17.3 on end # - I2C 7
+ device pci 18.0 on end # - UART 0
+ device pci 18.1 on end # - UART 1
+ device pci 18.2 on end # - UART 2
+ device pci 18.3 on end # - UART 3
+ device pci 19.0 on end # - SPI 0
+ device pci 19.1 on end # - SPI 1
+ device pci 19.2 on end # - SPI 2
+ device pci 1a.0 on end # - PWM
+ device pci 1b.0 on end # - SDCARD
+ device pci 1c.0 on end # - eMMC
+ device pci 1e.0 on end # - SDIO
+ device pci 1f.0 on end # - LPC
+ device pci 1f.1 on end # - SMBUS
+ end
+end
diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl
new file mode 100644
index 0000000..53a7b0f
--- /dev/null
+++ b/src/mainboard/intel/leafhill/dsdt.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ * (Written by Lijian Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 */
+ "COREv4", /* OEM id */
+ "COREBOOT", /* OEM table id */
+ 0x20110725 /* OEM revision */
+)
+{
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) /* PCIe */
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/apollolake/acpi/sleepstates.asl>
+
+}
diff --git a/src/mainboard/intel/leafhill/ibb_fmap.fmd b/src/mainboard/intel/leafhill/ibb_fmap.fmd
new file mode 100644
index 0000000..06e905c
--- /dev/null
+++ b/src/mainboard/intel/leafhill/ibb_fmap.fmd
@@ -0,0 +1,6 @@
+FLASH@##ROM_BASE## ##ROM_SIZE## {
+ BIOS@##BIOS_BASE## ##BIOS_SIZE## {
+ FMAP@##FMAP_BASE## ##FMAP_SIZE##
+ COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
+ }
+}
diff --git a/src/mainboard/intel/leafhill/obb_fmap.fmd b/src/mainboard/intel/leafhill/obb_fmap.fmd
new file mode 100644
index 0000000..d0d0720
--- /dev/null
+++ b/src/mainboard/intel/leafhill/obb_fmap.fmd
@@ -0,0 +1,6 @@
+FLASH at 0x200000 0x100000 {
+ BIOS at 0 0x100000 {
+ FMAP at 0 0x100
+ COREBOOT(CBFS)@0x100 1048320
+ }
+}
\ No newline at end of file
diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c
new file mode 100644
index 0000000..256570a
--- /dev/null
+++ b/src/mainboard/intel/leafhill/romstage.c
@@ -0,0 +1,128 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Intel Corp.
+ * (Written by Lance Zhao <lijian.zhao at intel.com> for Intel Corp.)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/romstage.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <FspmUpd.h>
+#include "board.h"
+#include "brd_gpio.h"
+
+static const uint8_t Ch0_Bit_swizzling[] = {
+ 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f,
+ 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03,
+ 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e,
+ 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15
+};
+static const uint8_t Ch1_Bit_swizzling[] = {
+ 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02,
+ 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f,
+ 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17,
+ 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f
+};
+static const uint8_t Ch2_Bit_swizzling[] = {
+ 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a,
+ 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04,
+ 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d,
+ 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11
+};
+static const uint8_t Ch3_Bit_swizzling[] = {
+ 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07,
+ 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d,
+ 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12,
+ 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ /* setup early gpio before memory */
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+
+ /* DRAM Config settings */
+ mupd->FspmConfig.Package = 0x1;
+ mupd->FspmConfig.Profile = 0xB;
+ mupd->FspmConfig.MemoryDown = 0x1;
+ mupd->FspmConfig.DDR3LPageSize = 0x0;
+ mupd->FspmConfig.DDR3LASR = 0x0;
+ mupd->FspmConfig.ScramblerSupport = 0x1;
+ mupd->FspmConfig.ChannelHashMask = 0x36;
+ mupd->FspmConfig.SliceHashMask = 0x9;
+ mupd->FspmConfig.InterleavedMode = 0x2;
+ mupd->FspmConfig.ChannelsSlicesEnable = 0x0;
+ mupd->FspmConfig.MinRefRate2xEnable = 0x0;
+ mupd->FspmConfig.DualRankSupportEnable = 0x1;
+ mupd->FspmConfig.RmtMode = 0x0;
+ mupd->FspmConfig.MemorySizeLimit = 0x1800;
+ mupd->FspmConfig.LowMemoryMaxValue = 0x0;
+ mupd->FspmConfig.DisableFastBoot = 0x0;
+ mupd->FspmConfig.HighMemoryMaxValue = 0x0;
+ mupd->FspmConfig.DIMM0SPDAddress = 0x0;
+ mupd->FspmConfig.DIMM1SPDAddress = 0x0;
+ mupd->FspmConfig.Ch0_RankEnable = 0x3;
+ mupd->FspmConfig.Ch0_DeviceWidth = 0x1;
+ mupd->FspmConfig.Ch0_DramDensity = 0x2;
+ mupd->FspmConfig.Ch0_Option = 0x3;
+ mupd->FspmConfig.Ch0_OdtConfig = 0x0;
+ mupd->FspmConfig.Ch0_TristateClk1 = 0x0;
+ mupd->FspmConfig.Ch0_Mode2N = 0x0;
+ mupd->FspmConfig.Ch0_OdtLevels = 0x0;
+ mupd->FspmConfig.Ch1_RankEnable = 0x3;
+ mupd->FspmConfig.Ch1_DeviceWidth = 0x1;
+ mupd->FspmConfig.Ch1_DramDensity = 0x2;
+ mupd->FspmConfig.Ch1_Option = 0x3;
+ mupd->FspmConfig.Ch1_OdtConfig = 0x0;
+ mupd->FspmConfig.Ch1_TristateClk1 = 0x0;
+ mupd->FspmConfig.Ch1_Mode2N = 0x0;
+ mupd->FspmConfig.Ch1_OdtLevels = 0x0;
+ mupd->FspmConfig.Ch2_RankEnable = 0x3;
+ mupd->FspmConfig.Ch2_DeviceWidth = 0x1;
+ mupd->FspmConfig.Ch2_DramDensity = 0x2;
+ mupd->FspmConfig.Ch2_Option = 0x3;
+ mupd->FspmConfig.Ch2_OdtConfig = 0x0;
+ mupd->FspmConfig.Ch2_TristateClk1 = 0x0;
+ mupd->FspmConfig.Ch2_Mode2N = 0x0;
+ mupd->FspmConfig.Ch2_OdtLevels = 0x0;
+ mupd->FspmConfig.Ch3_RankEnable = 0x3;
+ mupd->FspmConfig.Ch3_DeviceWidth = 0x1;
+ mupd->FspmConfig.Ch3_DramDensity = 0x2;
+ mupd->FspmConfig.Ch3_Option = 0x3;
+ mupd->FspmConfig.Ch3_OdtConfig = 0x0;
+ mupd->FspmConfig.Ch3_TristateClk1 = 0x0;
+ mupd->FspmConfig.Ch3_Mode2N = 0x0;
+ mupd->FspmConfig.Ch3_OdtLevels = 0x0;
+ mupd->FspmConfig.RmtCheckRun = 0x0;
+ mupd->FspmConfig.MrcDataSaving = 0x1;
+ mupd->FspmConfig.MrcFastBoot = 0x1;
+
+ memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling,
+ sizeof(Ch0_Bit_swizzling));
+ memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling,
+ sizeof(Ch1_Bit_swizzling));
+ memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling,
+ sizeof(Ch2_Bit_swizzling));
+ memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling,
+ sizeof(Ch3_Bit_swizzling));
+
+ mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0;
+ mupd->FspmConfig.MsgLevelMask = 0x0;
+
+ /* Request FSP to load the coreboot primary CBFS */
+ mupd->FspmConfig.OemLoadingBase = CONFIG_OBB_ROM_BASE;
+ strcpy((char *)mupd->FspmConfig.OemFileName, "OBB");
+
+}
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