[coreboot-gerrit] Patch set updated for coreboot: nb/intel/sandybridge/gma: Always initialize DP buffer translation

[Nico Huber (nico.h@gmx.de)]

Nico Huber (nico.h at gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17073

-gerrit

commit 19daa48201122dfc400eaef54999657e2f33a0a6
Author: Nico Huber <nico.huber at secunet.com>
Date:   Wed Oct 19 15:20:17 2016 +0200

    nb/intel/sandybridge/gma: Always initialize DP buffer translation
    
    These settings should be always made by the firmware, no matter if we
    set up graphics or not. It looks like Linux doesn't even know these
    registers.
    
    The values are taken from the PRMs for Sandy Bridge and Ivy Bridge [1,
    2]. They match the settings that were done in the native graphics path
    for Ivy Bridge. I expect the differences to be an update (i.e. the set-
    tings we did on the Sandy Bridge path were just outdated). Also, these
    settings affect the PCH and not the CPU which are independent from each
    other.
    
    [1] Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM)
        Volume 3 Part 3: PCH Display Registers (SandyBridge)
        Doc Ref #: IHD-OS-V3 Pt3 – 05 11
        https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3.pdf
    
    [2] Intel ® OpenSource HD Graphics Programmer’s Reference Manual (PRM)
        Volume 3 Part 4: South Display Engine Registers (Ivy Bridge)
        Doc Ref #: IHD-OS-V3 Pt 4 – 05 12
        https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf
    
    Change-Id: I83cc90c7558b93273a727f332fb0d8ced47ed70e
    Signed-off-by: Nico Huber <nico.huber at secunet.com>
---
 src/northbridge/intel/sandybridge/gma.c              | 12 ++++++++++++
 .../intel/sandybridge/gma_ivybridge_lvds.c           | 20 --------------------
 .../intel/sandybridge/gma_sandybridge_lvds.c         | 10 ----------
 3 files changed, 12 insertions(+), 30 deletions(-)

diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c
index f0d96ce..f050eb2 100644
--- a/src/northbridge/intel/sandybridge/gma.c
+++ b/src/northbridge/intel/sandybridge/gma.c
@@ -494,6 +494,18 @@ static void gma_pm_init_pre_vbios(struct device *dev)
 	reg32 = gtt_read(0x6c024);
 	reg32 &= ~0x000001c0;
 	gtt_write(0x6c024, reg32);
+
+	/* Initialize DP buffer translation with recommended defaults */
+	gtt_write(0xe4f00, 0x0100030c);
+	gtt_write(0xe4f04, 0x00b8230c);
+	gtt_write(0xe4f08, 0x06f8930c);
+	gtt_write(0xe4f0c, 0x05f8e38e);
+	gtt_write(0xe4f10, 0x00b8030c);
+	gtt_write(0xe4f14, 0x0b78830c);
+	gtt_write(0xe4f18, 0x09f8d3cf);
+	gtt_write(0xe4f1c, 0x01e8030c);
+	gtt_write(0xe4f20, 0x09f863cf);
+	gtt_write(0xe4f24, 0x0ff803cf);
 }
 
 static void gma_pm_init_post_vbios(struct device *dev)
diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
index 831e8ce..29dc76e 100644
--- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
@@ -76,16 +76,6 @@ static void enable_port(u8 *mmio)
 	write32(mmio + 0xf2060, 0x10);
 	write32(mmio + 0x9840, 0x0);
 	write32(mmio + 0x42000, 0xa0000000);
-	write32(mmio + 0xe4f00, 0x100030c);
-	write32(mmio + 0xe4f04, 0xb8230c);
-	write32(mmio + 0xe4f08, 0x6f8930c);
-	write32(mmio + 0xe4f0c, 0x5f8e38e);
-	write32(mmio + 0xe4f10, 0xb8030c);
-	write32(mmio + 0xe4f14, 0xb78830c);
-	write32(mmio + 0xe4f18, 0x9f8d3cf);
-	write32(mmio + 0xe4f1c, 0x1e8030c);
-	write32(mmio + 0xe4f20, 0x9f863cf);
-	write32(mmio + 0xe4f24, 0xff803cf);
 	read32(mmio + 0xe4100);
 	write32(mmio + 0xc4030, 0x10);
 	write32(mmio + 0xe4110, 0x8004003e);
@@ -115,16 +105,6 @@ static void enable_port(u8 *mmio)
 	read32(mmio + 0xe1140);
 	write32(mmio + 0xc4030, 0x10);
 	read32(mmio + 0xc4000);
-	write32(mmio + 0xe4f00, 0x100030c);
-	write32(mmio + 0xe4f04, 0xb8230c);
-	write32(mmio + 0xe4f08, 0x6f8930c);
-	write32(mmio + 0xe4f0c, 0x5f8e38e);
-	write32(mmio + 0xe4f10, 0xb8030c);
-	write32(mmio + 0xe4f14, 0xb78830c);
-	write32(mmio + 0xe4f18, 0x9f8d3cf);
-	write32(mmio + 0xe4f1c, 0x1e8030c);
-	write32(mmio + 0xe4f20, 0x9f863cf);
-	write32(mmio + 0xe4f24, 0xff803cf);
 	read32(mmio + 0xe4200);
 	write32(mmio + 0xc4030, 0x1010);
 	write32(mmio + 0xe4210, 0x8004003e);
diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
index c2c8087..acd90a2 100644
--- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
+++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
@@ -94,16 +94,6 @@ static void power_port(u8 *mmio)
 	read32(mmio + 0x000e4210); // = 0x5144003e
 	read32(mmio + 0x000e4210); // = 0x5144003e
 	write32(mmio + 0x000e4210, 0x5344003e);
-	write32(mmio + 0x000e4f00, 0x0100030c);
-	write32(mmio + 0x000e4f04, 0x00b8230c);
-	write32(mmio + 0x000e4f08, 0x06f8930c);
-	write32(mmio + 0x000e4f0c, 0x09f8e38e);
-	write32(mmio + 0x000e4f10, 0x00b8030c);
-	write32(mmio + 0x000e4f14, 0x0b78830c);
-	write32(mmio + 0x000e4f18, 0x0ff8d3cf);
-	write32(mmio + 0x000e4f1c, 0x01e8030c);
-	write32(mmio + 0x000e4f20, 0x0ff863cf);
-	write32(mmio + 0x000e4f24, 0x0ff803cf);
 	write32(mmio + 0x000c4030, 0x00001000);
 	read32(mmio + 0x000c4000); // = 0x00000000
 	write32(mmio + 0x000c4030, 0x00001000);