[coreboot-gerrit] New patch to review for coreboot: rockchip/rk3399: sdram: get index1 training value
Patrick Georgi (pgeorgi@google.com)
gerrit at coreboot.org
Mon Oct 24 12:11:46 CEST 2016
Patrick Georgi (pgeorgi at google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17104
-gerrit
commit 45f7e5c76b64ad0462ca6902205a1c259b20895b
Author: Lin Huang <hl at rock-chips.com>
Date: Thu Sep 15 22:59:55 2016 +0800
rockchip/rk3399: sdram: get index1 training value
if we want to do ddr dvfs in kernel, we need index0 and
index1 training value. We only save index0 training before,
we save index1 tarining value here.
BUG=None
BRANCH=None
TEST=Boot from kevin
Change-Id: I944a4b297a4ed6966893aa09553da88171307a42
Signed-off-by: Patrick Georgi <pgeorgi at chromium.org>
Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2
Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7
Original-Signed-off-by: Lin Huang <hl at rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386596
Original-Commit-Ready: Douglas Anderson <dianders at chromium.org>
Original-Reviewed-by: Derek Basehore <dbasehore at chromium.org>
Original-Reviewed-by: Julius Werner <jwerner at chromium.org>
---
.../gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 82 ++++++-------
.../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 134 ++++++++++-----------
.../gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 +-
src/soc/rockchip/rk3399/include/soc/addressmap.h | 2 +-
src/soc/rockchip/rk3399/include/soc/sdram.h | 12 ++
src/soc/rockchip/rk3399/sdram.c | 32 +++++
6 files changed, 156 insertions(+), 112 deletions(-)
diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c
index 4b73cb0..e1a517a 100644
--- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c
+++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c
@@ -70,10 +70,10 @@ struct rk3399_sdram_params params = {
0x000208d6, /* DENALI_CTL_06_DATA */
0x0000029b, /* DENALI_CTL_07_DATA */
0x00001a0b, /* DENALI_CTL_08_DATA */
- 0x00000028, /* DENALI_CTL_09_DATA */
- 0x00013880, /* DENALI_CTL_10_DATA */
- 0x00000190, /* DENALI_CTL_11_DATA */
- 0x00000fa0, /* DENALI_CTL_12_DATA */
+ 0x00000043, /* DENALI_CTL_09_DATA */
+ 0x000208d6, /* DENALI_CTL_10_DATA */
+ 0x0000029b, /* DENALI_CTL_11_DATA */
+ 0x00001a0b, /* DENALI_CTL_12_DATA */
0x00000043, /* DENALI_CTL_13_DATA */
0x000208d6, /* DENALI_CTL_14_DATA */
0x0000029b, /* DENALI_CTL_15_DATA */
@@ -89,40 +89,40 @@ struct rk3399_sdram_params params = {
0x04000614, /* DENALI_CTL_25_DATA */
0x2a070004, /* DENALI_CTL_26_DATA */
0x220c051c, /* DENALI_CTL_27_DATA */
- 0x111a0400, /* DENALI_CTL_28_DATA */
- 0x00140804, /* DENALI_CTL_29_DATA */
+ 0x1c2a0700, /* DENALI_CTL_28_DATA */
+ 0x00220c05, /* DENALI_CTL_29_DATA */
0x051c2a07, /* DENALI_CTL_30_DATA */
0x0500220c, /* DENALI_CTL_31_DATA */
0x00000a0a, /* DENALI_CTL_32_DATA */
0x0500b64a, /* DENALI_CTL_33_DATA */
- 0x0a0a040a, /* DENALI_CTL_34_DATA */
- 0x03006d60, /* DENALI_CTL_35_DATA */
- 0x0a0a0506, /* DENALI_CTL_36_DATA */
+ 0x0a0a050a, /* DENALI_CTL_34_DATA */
+ 0x0500b64a, /* DENALI_CTL_35_DATA */
+ 0x0a0a050a, /* DENALI_CTL_36_DATA */
0x0500b64a, /* DENALI_CTL_37_DATA */
0x0203000a, /* DENALI_CTL_38_DATA */
- 0x080a0c00, /* DENALI_CTL_39_DATA */
- 0x040a0c06, /* DENALI_CTL_40_DATA */
+ 0x0c0a0c00, /* DENALI_CTL_39_DATA */
+ 0x040a0c0a, /* DENALI_CTL_40_DATA */
0x14000a0a, /* DENALI_CTL_41_DATA */
0x02020a0a, /* DENALI_CTL_42_DATA */
0x00010002, /* DENALI_CTL_43_DATA */
- 0x03160e16, /* DENALI_CTL_44_DATA */
- 0x000e090e, /* DENALI_CTL_45_DATA */
+ 0x03161616, /* DENALI_CTL_44_DATA */
+ 0x000e0e0e, /* DENALI_CTL_45_DATA */
0x00000000, /* DENALI_CTL_46_DATA */
0x03010000, /* DENALI_CTL_47_DATA */
0x0a20008c, /* DENALI_CTL_48_DATA */
- 0x06100054, /* DENALI_CTL_49_DATA */
+ 0x0a20008c, /* DENALI_CTL_49_DATA */
0x0a20008c, /* DENALI_CTL_50_DATA */
0x00000000, /* DENALI_CTL_51_DATA */
- 0x00030005, /* DENALI_CTL_52_DATA */
+ 0x00050005, /* DENALI_CTL_52_DATA */
0x00100005, /* DENALI_CTL_53_DATA */
- 0x0010000a, /* DENALI_CTL_54_DATA */
- 0x000c080c, /* DENALI_CTL_55_DATA */
+ 0x00100010, /* DENALI_CTL_54_DATA */
+ 0x000c0c0c, /* DENALI_CTL_55_DATA */
0x00000000, /* DENALI_CTL_56_DATA */
0x00000000, /* DENALI_CTL_57_DATA */
0x00000000, /* DENALI_CTL_58_DATA */
0x00930000, /* DENALI_CTL_59_DATA */
- 0x00580093, /* DENALI_CTL_60_DATA */
- 0x00930058, /* DENALI_CTL_61_DATA */
+ 0x00930093, /* DENALI_CTL_60_DATA */
+ 0x00930093, /* DENALI_CTL_61_DATA */
0x00000093, /* DENALI_CTL_62_DATA */
0x00000000, /* DENALI_CTL_63_DATA */
0x00000000, /* DENALI_CTL_64_DATA */
@@ -145,7 +145,7 @@ struct rk3399_sdram_params params = {
0x00040005, /* DENALI_CTL_81_DATA */
0x28800000, /* DENALI_CTL_82_DATA */
0x00001440, /* DENALI_CTL_83_DATA */
- 0x0c201840, /* DENALI_CTL_84_DATA */
+ 0x14402880, /* DENALI_CTL_84_DATA */
0x28800000, /* DENALI_CTL_85_DATA */
0x00001440, /* DENALI_CTL_86_DATA */
0x00000000, /* DENALI_CTL_87_DATA */
@@ -186,9 +186,9 @@ struct rk3399_sdram_params params = {
0x00860000, /* DENALI_CTL_122_DATA */
0x00a70043, /* DENALI_CTL_123_DATA */
0x00a70000, /* DENALI_CTL_124_DATA */
- 0x00280050, /* DENALI_CTL_125_DATA */
- 0x00000064, /* DENALI_CTL_126_DATA */
- 0x00860064, /* DENALI_CTL_127_DATA */
+ 0x00430086, /* DENALI_CTL_125_DATA */
+ 0x000000a7, /* DENALI_CTL_126_DATA */
+ 0x008600a7, /* DENALI_CTL_127_DATA */
0x00a70043, /* DENALI_CTL_128_DATA */
0x00a70000, /* DENALI_CTL_129_DATA */
0x00000000, /* DENALI_CTL_130_DATA */
@@ -196,12 +196,12 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_132_DATA */
0x00030000, /* DENALI_CTL_133_DATA */
0x00000018, /* DENALI_CTL_134_DATA */
- 0x00080083, /* DENALI_CTL_135_DATA */
+ 0x00180003, /* DENALI_CTL_135_DATA */
0x00030000, /* DENALI_CTL_136_DATA */
0x00000018, /* DENALI_CTL_137_DATA */
0x00010001, /* DENALI_CTL_138_DATA */
0x06000001, /* DENALI_CTL_139_DATA */
- 0x00000707, /* DENALI_CTL_140_DATA */
+ 0x00000706, /* DENALI_CTL_140_DATA */
0x00000000, /* DENALI_CTL_141_DATA */
0x00000000, /* DENALI_CTL_142_DATA */
0x00000000, /* DENALI_CTL_143_DATA */
@@ -210,12 +210,12 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_146_DATA */
0x00030000, /* DENALI_CTL_147_DATA */
0x00000018, /* DENALI_CTL_148_DATA */
- 0x00080083, /* DENALI_CTL_149_DATA */
+ 0x00180003, /* DENALI_CTL_149_DATA */
0x00030000, /* DENALI_CTL_150_DATA */
0x00000018, /* DENALI_CTL_151_DATA */
0x00010001, /* DENALI_CTL_152_DATA */
0x06000001, /* DENALI_CTL_153_DATA */
- 0x00000707, /* DENALI_CTL_154_DATA */
+ 0x00000706, /* DENALI_CTL_154_DATA */
0x00000000, /* DENALI_CTL_155_DATA */
0x00000000, /* DENALI_CTL_156_DATA */
0x00000000, /* DENALI_CTL_157_DATA */
@@ -243,13 +243,13 @@ struct rk3399_sdram_params params = {
0x00029b03, /* DENALI_CTL_179_DATA */
0x003c00f0, /* DENALI_CTL_180_DATA */
0x00000000, /* DENALI_CTL_181_DATA */
- 0x00900190, /* DENALI_CTL_182_DATA */
- 0x00000024, /* DENALI_CTL_183_DATA */
+ 0x00f0029b, /* DENALI_CTL_182_DATA */
+ 0x0000003c, /* DENALI_CTL_183_DATA */
0x00029b00, /* DENALI_CTL_184_DATA */
0x003c00f0, /* DENALI_CTL_185_DATA */
0x00000000, /* DENALI_CTL_186_DATA */
0x00220000, /* DENALI_CTL_187_DATA */
- 0x00220014, /* DENALI_CTL_188_DATA */
+ 0x00220022, /* DENALI_CTL_188_DATA */
0x01010100, /* DENALI_CTL_189_DATA */
0x01000202, /* DENALI_CTL_190_DATA */
0x0a000002, /* DENALI_CTL_191_DATA */
@@ -273,17 +273,17 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_209_DATA */
0x00000000, /* DENALI_CTL_210_DATA */
0x00010000, /* DENALI_CTL_211_DATA */
- 0x03020301, /* DENALI_CTL_212_DATA */
+ 0x03030301, /* DENALI_CTL_212_DATA */
0x01010808, /* DENALI_CTL_213_DATA */
- 0x04030001, /* DENALI_CTL_214_DATA */
+ 0x03030001, /* DENALI_CTL_214_DATA */
0x08080803, /* DENALI_CTL_215_DATA */
0x08080808, /* DENALI_CTL_216_DATA */
- 0x02050203, /* DENALI_CTL_217_DATA */
- 0x02050303, /* DENALI_CTL_218_DATA */
+ 0x08050203, /* DENALI_CTL_217_DATA */
+ 0x02050203, /* DENALI_CTL_218_DATA */
0x00050203, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */
- 0x03020400, /* DENALI_CTL_221_DATA */
- 0x00020401, /* DENALI_CTL_222_DATA */
+ 0x04020400, /* DENALI_CTL_221_DATA */
+ 0x00020402, /* DENALI_CTL_222_DATA */
0x00000000, /* DENALI_CTL_223_DATA */
0x00000000, /* DENALI_CTL_224_DATA */
0x0d000001, /* DENALI_CTL_225_DATA */
@@ -336,7 +336,7 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_272_DATA */
0x00000000, /* DENALI_CTL_273_DATA */
0x00ffff00, /* DENALI_CTL_274_DATA */
- 0x181b0000, /* DENALI_CTL_275_DATA */
+ 0x1b1b0000, /* DENALI_CTL_275_DATA */
0x0800001b, /* DENALI_CTL_276_DATA */
0x00001440, /* DENALI_CTL_277_DATA */
0x00000200, /* DENALI_CTL_278_DATA */
@@ -345,13 +345,13 @@ struct rk3399_sdram_params params = {
0x00000200, /* DENALI_CTL_281_DATA */
0x00001440, /* DENALI_CTL_282_DATA */
0x0000ca80, /* DENALI_CTL_283_DATA */
- 0x0c200509, /* DENALI_CTL_284_DATA */
+ 0x14400509, /* DENALI_CTL_284_DATA */
0x00000200, /* DENALI_CTL_285_DATA */
0x00000200, /* DENALI_CTL_286_DATA */
0x00000200, /* DENALI_CTL_287_DATA */
0x00000200, /* DENALI_CTL_288_DATA */
- 0x00000c20, /* DENALI_CTL_289_DATA */
- 0x00007940, /* DENALI_CTL_290_DATA */
+ 0x00001440, /* DENALI_CTL_289_DATA */
+ 0x0000ca80, /* DENALI_CTL_290_DATA */
0x14400509, /* DENALI_CTL_291_DATA */
0x00000200, /* DENALI_CTL_292_DATA */
0x00000200, /* DENALI_CTL_293_DATA */
@@ -370,7 +370,7 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_306_DATA */
0x00030000, /* DENALI_CTL_307_DATA */
0x000d001f, /* DENALI_CTL_308_DATA */
- 0x000a001c, /* DENALI_CTL_309_DATA */
+ 0x000d001f, /* DENALI_CTL_309_DATA */
0x000d001f, /* DENALI_CTL_310_DATA */
0x00000000, /* DENALI_CTL_311_DATA */
0x00000000, /* DENALI_CTL_312_DATA */
diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c
index 3056e55..1035d5d 100644
--- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c
+++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c
@@ -70,10 +70,10 @@ struct rk3399_sdram_params params = {
0x00027100, /* DENALI_CTL_06_DATA */
0x00000320, /* DENALI_CTL_07_DATA */
0x00001f40, /* DENALI_CTL_08_DATA */
- 0x00000028, /* DENALI_CTL_09_DATA */
- 0x00013880, /* DENALI_CTL_10_DATA */
- 0x00000190, /* DENALI_CTL_11_DATA */
- 0x00000fa0, /* DENALI_CTL_12_DATA */
+ 0x00000050, /* DENALI_CTL_09_DATA */
+ 0x00027100, /* DENALI_CTL_10_DATA */
+ 0x00000320, /* DENALI_CTL_11_DATA */
+ 0x00001f40, /* DENALI_CTL_12_DATA */
0x00000050, /* DENALI_CTL_13_DATA */
0x00027100, /* DENALI_CTL_14_DATA */
0x00000320, /* DENALI_CTL_15_DATA */
@@ -89,40 +89,40 @@ struct rk3399_sdram_params params = {
0x04000618, /* DENALI_CTL_25_DATA */
0x33080004, /* DENALI_CTL_26_DATA */
0x280f0622, /* DENALI_CTL_27_DATA */
- 0x111a0400, /* DENALI_CTL_28_DATA */
- 0x00140804, /* DENALI_CTL_29_DATA */
+ 0x22330800, /* DENALI_CTL_28_DATA */
+ 0x00280f06, /* DENALI_CTL_29_DATA */
0x06223308, /* DENALI_CTL_30_DATA */
0x0600280f, /* DENALI_CTL_31_DATA */
0x00000a0a, /* DENALI_CTL_32_DATA */
0x0600dac0, /* DENALI_CTL_33_DATA */
- 0x0a0a040c, /* DENALI_CTL_34_DATA */
- 0x03006d60, /* DENALI_CTL_35_DATA */
- 0x0a0a0606, /* DENALI_CTL_36_DATA */
+ 0x0a0a060c, /* DENALI_CTL_34_DATA */
+ 0x0600dac0, /* DENALI_CTL_35_DATA */
+ 0x0a0a060c, /* DENALI_CTL_36_DATA */
0x0600dac0, /* DENALI_CTL_37_DATA */
0x0203000c, /* DENALI_CTL_38_DATA */
- 0x080c0f00, /* DENALI_CTL_39_DATA */
- 0x040c0f06, /* DENALI_CTL_40_DATA */
+ 0x0f0c0f00, /* DENALI_CTL_39_DATA */
+ 0x040c0f0c, /* DENALI_CTL_40_DATA */
0x14000a0a, /* DENALI_CTL_41_DATA */
- 0x02030a0a, /* DENALI_CTL_42_DATA */
+ 0x03030a0a, /* DENALI_CTL_42_DATA */
0x00010003, /* DENALI_CTL_43_DATA */
- 0x031b0e1b, /* DENALI_CTL_44_DATA */
- 0x00110911, /* DENALI_CTL_45_DATA */
+ 0x031b1b1b, /* DENALI_CTL_44_DATA */
+ 0x00111111, /* DENALI_CTL_45_DATA */
0x00000000, /* DENALI_CTL_46_DATA */
0x03010000, /* DENALI_CTL_47_DATA */
0x0c2800a8, /* DENALI_CTL_48_DATA */
- 0x06100054, /* DENALI_CTL_49_DATA */
+ 0x0c2800a8, /* DENALI_CTL_49_DATA */
0x0c2800a8, /* DENALI_CTL_50_DATA */
0x00000000, /* DENALI_CTL_51_DATA */
- 0x00030006, /* DENALI_CTL_52_DATA */
+ 0x00060006, /* DENALI_CTL_52_DATA */
0x00140006, /* DENALI_CTL_53_DATA */
- 0x0014000a, /* DENALI_CTL_54_DATA */
- 0x000f080f, /* DENALI_CTL_55_DATA */
+ 0x00140014, /* DENALI_CTL_54_DATA */
+ 0x000f0f0f, /* DENALI_CTL_55_DATA */
0x00000000, /* DENALI_CTL_56_DATA */
0x00000000, /* DENALI_CTL_57_DATA */
0x00000000, /* DENALI_CTL_58_DATA */
0x00b00000, /* DENALI_CTL_59_DATA */
- 0x005800b0, /* DENALI_CTL_60_DATA */
- 0x00b00058, /* DENALI_CTL_61_DATA */
+ 0x00b000b0, /* DENALI_CTL_60_DATA */
+ 0x00b000b0, /* DENALI_CTL_61_DATA */
0x000000b0, /* DENALI_CTL_62_DATA */
0x00000000, /* DENALI_CTL_63_DATA */
0x00000000, /* DENALI_CTL_64_DATA */
@@ -145,7 +145,7 @@ struct rk3399_sdram_params params = {
0x00040005, /* DENALI_CTL_81_DATA */
0x30a00000, /* DENALI_CTL_82_DATA */
0x00001850, /* DENALI_CTL_83_DATA */
- 0x0c201840, /* DENALI_CTL_84_DATA */
+ 0x185030a0, /* DENALI_CTL_84_DATA */
0x30a00000, /* DENALI_CTL_85_DATA */
0x00001850, /* DENALI_CTL_86_DATA */
0x00000000, /* DENALI_CTL_87_DATA */
@@ -186,9 +186,9 @@ struct rk3399_sdram_params params = {
0x00a00000, /* DENALI_CTL_122_DATA */
0x00c80050, /* DENALI_CTL_123_DATA */
0x00c80000, /* DENALI_CTL_124_DATA */
- 0x00280050, /* DENALI_CTL_125_DATA */
- 0x00000064, /* DENALI_CTL_126_DATA */
- 0x00a00064, /* DENALI_CTL_127_DATA */
+ 0x005000a0, /* DENALI_CTL_125_DATA */
+ 0x000000c8, /* DENALI_CTL_126_DATA */
+ 0x00a000c8, /* DENALI_CTL_127_DATA */
0x00c80050, /* DENALI_CTL_128_DATA */
0x00c80000, /* DENALI_CTL_129_DATA */
0x00000000, /* DENALI_CTL_130_DATA */
@@ -196,12 +196,12 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_132_DATA */
0x00430000, /* DENALI_CTL_133_DATA */
0x0000001a, /* DENALI_CTL_134_DATA */
- 0x000a0083, /* DENALI_CTL_135_DATA */
+ 0x001a0043, /* DENALI_CTL_135_DATA */
0x00430000, /* DENALI_CTL_136_DATA */
0x0000001a, /* DENALI_CTL_137_DATA */
0x00010001, /* DENALI_CTL_138_DATA */
0x06000001, /* DENALI_CTL_139_DATA */
- 0x00000707, /* DENALI_CTL_140_DATA */
+ 0x00000706, /* DENALI_CTL_140_DATA */
0x00000000, /* DENALI_CTL_141_DATA */
0x00000000, /* DENALI_CTL_142_DATA */
0x00000000, /* DENALI_CTL_143_DATA */
@@ -210,12 +210,12 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_146_DATA */
0x00430000, /* DENALI_CTL_147_DATA */
0x0000001a, /* DENALI_CTL_148_DATA */
- 0x000a0083, /* DENALI_CTL_149_DATA */
+ 0x001a0043, /* DENALI_CTL_149_DATA */
0x00430000, /* DENALI_CTL_150_DATA */
0x0000001a, /* DENALI_CTL_151_DATA */
0x00010001, /* DENALI_CTL_152_DATA */
0x06000001, /* DENALI_CTL_153_DATA */
- 0x00000707, /* DENALI_CTL_154_DATA */
+ 0x00000706, /* DENALI_CTL_154_DATA */
0x00000000, /* DENALI_CTL_155_DATA */
0x00000000, /* DENALI_CTL_156_DATA */
0x00000000, /* DENALI_CTL_157_DATA */
@@ -243,13 +243,13 @@ struct rk3399_sdram_params params = {
0x00032003, /* DENALI_CTL_179_DATA */
0x00480120, /* DENALI_CTL_180_DATA */
0x00000000, /* DENALI_CTL_181_DATA */
- 0x00900190, /* DENALI_CTL_182_DATA */
- 0x00000024, /* DENALI_CTL_183_DATA */
+ 0x01200320, /* DENALI_CTL_182_DATA */
+ 0x00000048, /* DENALI_CTL_183_DATA */
0x00032000, /* DENALI_CTL_184_DATA */
0x00480120, /* DENALI_CTL_185_DATA */
0x00000000, /* DENALI_CTL_186_DATA */
0x00280000, /* DENALI_CTL_187_DATA */
- 0x00280014, /* DENALI_CTL_188_DATA */
+ 0x00280028, /* DENALI_CTL_188_DATA */
0x01010100, /* DENALI_CTL_189_DATA */
0x01000202, /* DENALI_CTL_190_DATA */
0x0a000002, /* DENALI_CTL_191_DATA */
@@ -273,17 +273,17 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_209_DATA */
0x00000000, /* DENALI_CTL_210_DATA */
0x00010000, /* DENALI_CTL_211_DATA */
- 0x03020301, /* DENALI_CTL_212_DATA */
+ 0x03030301, /* DENALI_CTL_212_DATA */
0x01010808, /* DENALI_CTL_213_DATA */
- 0x04030001, /* DENALI_CTL_214_DATA */
+ 0x03030001, /* DENALI_CTL_214_DATA */
0x0a0a0a03, /* DENALI_CTL_215_DATA */
0x08080808, /* DENALI_CTL_216_DATA */
- 0x02050103, /* DENALI_CTL_217_DATA */
+ 0x08050103, /* DENALI_CTL_217_DATA */
0x02050103, /* DENALI_CTL_218_DATA */
0x00050103, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */
- 0x03020500, /* DENALI_CTL_221_DATA */
- 0x00020501, /* DENALI_CTL_222_DATA */
+ 0x05020500, /* DENALI_CTL_221_DATA */
+ 0x00020502, /* DENALI_CTL_222_DATA */
0x00000000, /* DENALI_CTL_223_DATA */
0x00000000, /* DENALI_CTL_224_DATA */
0x0d000001, /* DENALI_CTL_225_DATA */
@@ -336,7 +336,7 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_272_DATA */
0x00000000, /* DENALI_CTL_273_DATA */
0x00ffff00, /* DENALI_CTL_274_DATA */
- 0x181e0000, /* DENALI_CTL_275_DATA */
+ 0x1e1e0000, /* DENALI_CTL_275_DATA */
0x0800001e, /* DENALI_CTL_276_DATA */
0x00001850, /* DENALI_CTL_277_DATA */
0x00000200, /* DENALI_CTL_278_DATA */
@@ -345,14 +345,14 @@ struct rk3399_sdram_params params = {
0x00000200, /* DENALI_CTL_281_DATA */
0x00001850, /* DENALI_CTL_282_DATA */
0x0000f320, /* DENALI_CTL_283_DATA */
- 0x0c20050a, /* DENALI_CTL_284_DATA */
+ 0x1850050a, /* DENALI_CTL_284_DATA */
0x00000200, /* DENALI_CTL_285_DATA */
0x00000200, /* DENALI_CTL_286_DATA */
0x00000200, /* DENALI_CTL_287_DATA */
0x00000200, /* DENALI_CTL_288_DATA */
- 0x00000c20, /* DENALI_CTL_289_DATA */
- 0x00007940, /* DENALI_CTL_290_DATA */
- 0x1850050b, /* DENALI_CTL_291_DATA */
+ 0x00001850, /* DENALI_CTL_289_DATA */
+ 0x0000f320, /* DENALI_CTL_290_DATA */
+ 0x1850050a, /* DENALI_CTL_291_DATA */
0x00000200, /* DENALI_CTL_292_DATA */
0x00000200, /* DENALI_CTL_293_DATA */
0x00000200, /* DENALI_CTL_294_DATA */
@@ -370,7 +370,7 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_CTL_306_DATA */
0x00030000, /* DENALI_CTL_307_DATA */
0x000e0020, /* DENALI_CTL_308_DATA */
- 0x000a001c, /* DENALI_CTL_309_DATA */
+ 0x000e0020, /* DENALI_CTL_309_DATA */
0x000e0020, /* DENALI_CTL_310_DATA */
0x00000000, /* DENALI_CTL_311_DATA */
0x00000000, /* DENALI_CTL_312_DATA */
@@ -401,15 +401,15 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_01_DATA */
0x000030a0, /* DENALI_PI_02_DATA */
0x00001850, /* DENALI_PI_03_DATA */
- 0x00001840, /* DENALI_PI_04_DATA */
- 0x00000c20, /* DENALI_PI_05_DATA */
+ 0x000030a0, /* DENALI_PI_04_DATA */
+ 0x00001850, /* DENALI_PI_05_DATA */
0x000030a0, /* DENALI_PI_06_DATA */
0x18501850, /* DENALI_PI_07_DATA */
0x00000200, /* DENALI_PI_08_DATA */
0x00000200, /* DENALI_PI_09_DATA */
0x00000200, /* DENALI_PI_10_DATA */
0x00000200, /* DENALI_PI_11_DATA */
- 0x00000c20, /* DENALI_PI_12_DATA */
+ 0x00001850, /* DENALI_PI_12_DATA */
0x00000200, /* DENALI_PI_13_DATA */
0x00000200, /* DENALI_PI_14_DATA */
0x00000200, /* DENALI_PI_15_DATA */
@@ -439,12 +439,12 @@ struct rk3399_sdram_params params = {
0x0f000010, /* DENALI_PI_39_DATA */
0x377ff000, /* DENALI_PI_40_DATA */
0x03000101, /* DENALI_PI_41_DATA */
- 0x042e292e, /* DENALI_PI_42_DATA */
+ 0x042e2e2e, /* DENALI_PI_42_DATA */
0x06180006, /* DENALI_PI_43_DATA */
0x00061800, /* DENALI_PI_44_DATA */
0x00000018, /* DENALI_PI_45_DATA */
0x0c2800a8, /* DENALI_PI_46_DATA */
- 0x06100054, /* DENALI_PI_47_DATA */
+ 0x0c2800a8, /* DENALI_PI_47_DATA */
0x0c2800a8, /* DENALI_PI_48_DATA */
0x00000500, /* DENALI_PI_49_DATA */
0x00000000, /* DENALI_PI_50_DATA */
@@ -464,12 +464,12 @@ struct rk3399_sdram_params params = {
0x00000000, /* DENALI_PI_64_DATA */
0x00000000, /* DENALI_PI_65_DATA */
0x03060002, /* DENALI_PI_66_DATA */
- 0x03010201, /* DENALI_PI_67_DATA */
+ 0x03010301, /* DENALI_PI_67_DATA */
0x01080801, /* DENALI_PI_68_DATA */
0x04020201, /* DENALI_PI_69_DATA */
0x01080804, /* DENALI_PI_70_DATA */
0x00000000, /* DENALI_PI_71_DATA */
- 0x04030000, /* DENALI_PI_72_DATA */
+ 0x03030000, /* DENALI_PI_72_DATA */
0x0a0a0a03, /* DENALI_PI_73_DATA */
0x00000000, /* DENALI_PI_74_DATA */
0x00000000, /* DENALI_PI_75_DATA */
@@ -486,21 +486,21 @@ struct rk3399_sdram_params params = {
0x55555a5a, /* DENALI_PI_86_DATA */
0x55555a5a, /* DENALI_PI_87_DATA */
0x55555a5a, /* DENALI_PI_88_DATA */
- 0x0b0a0001, /* DENALI_PI_89_DATA */
+ 0x0a0a0001, /* DENALI_PI_89_DATA */
0x0505000a, /* DENALI_PI_90_DATA */
0x00000005, /* DENALI_PI_91_DATA */
0x00000100, /* DENALI_PI_92_DATA */
0x00030000, /* DENALI_PI_93_DATA */
0x17030000, /* DENALI_PI_94_DATA */
0x000e0020, /* DENALI_PI_95_DATA */
- 0x000a001c, /* DENALI_PI_96_DATA */
+ 0x000e0020, /* DENALI_PI_96_DATA */
0x000e0020, /* DENALI_PI_97_DATA */
0x00000000, /* DENALI_PI_98_DATA */
0x00000000, /* DENALI_PI_99_DATA */
0x00000100, /* DENALI_PI_100_DATA */
0x140a0000, /* DENALI_PI_101_DATA */
0x000a030a, /* DENALI_PI_102_DATA */
- 0x03000a02, /* DENALI_PI_103_DATA */
+ 0x03000a03, /* DENALI_PI_103_DATA */
0x010a000a, /* DENALI_PI_104_DATA */
0x00000100, /* DENALI_PI_105_DATA */
0x01000000, /* DENALI_PI_106_DATA */
@@ -508,12 +508,12 @@ struct rk3399_sdram_params params = {
0x00000100, /* DENALI_PI_108_DATA */
0x1e1a0000, /* DENALI_PI_109_DATA */
0x10010204, /* DENALI_PI_110_DATA */
- 0x07060705, /* DENALI_PI_111_DATA */
+ 0x07070705, /* DENALI_PI_111_DATA */
0x20000202, /* DENALI_PI_112_DATA */
0x00201000, /* DENALI_PI_113_DATA */
0x00201000, /* DENALI_PI_114_DATA */
0x04041000, /* DENALI_PI_115_DATA */
- 0x0c100100, /* DENALI_PI_116_DATA */
+ 0x10100100, /* DENALI_PI_116_DATA */
0x00010110, /* DENALI_PI_117_DATA */
0x004b004a, /* DENALI_PI_118_DATA */
0x1a030000, /* DENALI_PI_119_DATA */
@@ -525,43 +525,43 @@ struct rk3399_sdram_params params = {
0x00004300, /* DENALI_PI_125_DATA */
0x0001001a, /* DENALI_PI_126_DATA */
0x004d4d07, /* DENALI_PI_127_DATA */
- 0x000a0083, /* DENALI_PI_128_DATA */
+ 0x001a0043, /* DENALI_PI_128_DATA */
0x4d070001, /* DENALI_PI_129_DATA */
0x0000434d, /* DENALI_PI_130_DATA */
0x0001001a, /* DENALI_PI_131_DATA */
0x004d4d07, /* DENALI_PI_132_DATA */
0x001a0043, /* DENALI_PI_133_DATA */
0x4d070001, /* DENALI_PI_134_DATA */
- 0x0000834d, /* DENALI_PI_135_DATA */
- 0x0001000a, /* DENALI_PI_136_DATA */
+ 0x0000434d, /* DENALI_PI_135_DATA */
+ 0x0001001a, /* DENALI_PI_136_DATA */
0x004d4d07, /* DENALI_PI_137_DATA */
0x001a0043, /* DENALI_PI_138_DATA */
0x4d070001, /* DENALI_PI_139_DATA */
0x0043004d, /* DENALI_PI_140_DATA */
0x0001001a, /* DENALI_PI_141_DATA */
0x004d4d07, /* DENALI_PI_142_DATA */
- 0x000a0083, /* DENALI_PI_143_DATA */
+ 0x001a0043, /* DENALI_PI_143_DATA */
0x4d070001, /* DENALI_PI_144_DATA */
0x0000434d, /* DENALI_PI_145_DATA */
0x0001001a, /* DENALI_PI_146_DATA */
0x004d4d07, /* DENALI_PI_147_DATA */
0x001a0043, /* DENALI_PI_148_DATA */
0x4d070001, /* DENALI_PI_149_DATA */
- 0x0000834d, /* DENALI_PI_150_DATA */
- 0x0001000a, /* DENALI_PI_151_DATA */
+ 0x0000434d, /* DENALI_PI_150_DATA */
+ 0x0001001a, /* DENALI_PI_151_DATA */
0x004d4d07, /* DENALI_PI_152_DATA */
0x001a0043, /* DENALI_PI_153_DATA */
0x4d070001, /* DENALI_PI_154_DATA */
0x0100004d, /* DENALI_PI_155_DATA */
- 0x006400c8, /* DENALI_PI_156_DATA */
+ 0x00c800c8, /* DENALI_PI_156_DATA */
0x060400c8, /* DENALI_PI_157_DATA */
0x0c060f11, /* DENALI_PI_158_DATA */
0x2200d890, /* DENALI_PI_159_DATA */
0x0a0c2005, /* DENALI_PI_160_DATA */
- 0x0809040a, /* DENALI_PI_161_DATA */
- 0x00000604, /* DENALI_PI_162_DATA */
- 0x11006c48, /* DENALI_PI_163_DATA */
- 0x0a062003, /* DENALI_PI_164_DATA */
+ 0x0f11060a, /* DENALI_PI_161_DATA */
+ 0x00000c06, /* DENALI_PI_162_DATA */
+ 0x2200d890, /* DENALI_PI_163_DATA */
+ 0x0a0c2005, /* DENALI_PI_164_DATA */
0x0f11060a, /* DENALI_PI_165_DATA */
0x00000c06, /* DENALI_PI_166_DATA */
0x2200d890, /* DENALI_PI_167_DATA */
@@ -586,8 +586,8 @@ struct rk3399_sdram_params params = {
0x01000300, /* DENALI_PI_186_DATA */
0x00185000, /* DENALI_PI_187_DATA */
0x0000f320, /* DENALI_PI_188_DATA */
- 0x00000c20, /* DENALI_PI_189_DATA */
- 0x00007940, /* DENALI_PI_190_DATA */
+ 0x00001850, /* DENALI_PI_189_DATA */
+ 0x0000f320, /* DENALI_PI_190_DATA */
0x00001850, /* DENALI_PI_191_DATA */
0x0000f320, /* DENALI_PI_192_DATA */
0x08000000, /* DENALI_PI_193_DATA */
diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c
index 3947881..7110748 100644
--- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c
+++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c
@@ -201,7 +201,7 @@ struct rk3399_sdram_params params = {
0x0000001c, /* DENALI_CTL_137_DATA */
0x00010001, /* DENALI_CTL_138_DATA */
0x06000001, /* DENALI_CTL_139_DATA */
- 0x00000707, /* DENALI_CTL_140_DATA */
+ 0x00000606, /* DENALI_CTL_140_DATA */
0x00000000, /* DENALI_CTL_141_DATA */
0x00000000, /* DENALI_CTL_142_DATA */
0x00000000, /* DENALI_CTL_143_DATA */
@@ -215,7 +215,7 @@ struct rk3399_sdram_params params = {
0x0000001c, /* DENALI_CTL_151_DATA */
0x00010001, /* DENALI_CTL_152_DATA */
0x06000001, /* DENALI_CTL_153_DATA */
- 0x00000707, /* DENALI_CTL_154_DATA */
+ 0x00000606, /* DENALI_CTL_154_DATA */
0x00000000, /* DENALI_CTL_155_DATA */
0x00000000, /* DENALI_CTL_156_DATA */
0x00000000, /* DENALI_CTL_157_DATA */
@@ -278,7 +278,7 @@ struct rk3399_sdram_params params = {
0x04040001, /* DENALI_CTL_214_DATA */
0x0c0c0c04, /* DENALI_CTL_215_DATA */
0x08080808, /* DENALI_CTL_216_DATA */
- 0x02050103, /* DENALI_CTL_217_DATA */
+ 0x08050103, /* DENALI_CTL_217_DATA */
0x02050103, /* DENALI_CTL_218_DATA */
0x00050103, /* DENALI_CTL_219_DATA */
0x00020202, /* DENALI_CTL_220_DATA */
diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h
index d316c38..1762a8d 100644
--- a/src/soc/rockchip/rk3399/include/soc/addressmap.h
+++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h
@@ -17,7 +17,6 @@
#define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__
#define MAX_DRAM_ADDRESS 0xF8000000
-
#define PMUGRF_BASE 0xff320000
#define PMUSGRF_BASE 0xff330000
#define PMUCRU_BASE 0xff750000
@@ -69,6 +68,7 @@
#define SERVER_MSCH0_BASE_ADDR 0xffa84000
#define DDRC1_BASE_ADDR 0xffa88000
#define SERVER_MSCH1_BASE_ADDR 0xffa8c000
+#define CIC_BASE_ADDR 0xff620000
#define USB_OTG0_DWC3_BASE 0xfe80c100
#define USB_OTG1_DWC3_BASE 0xfe90c100
diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h
index 1ec6d39..bf99b35 100644
--- a/src/soc/rockchip/rk3399/include/soc/sdram.h
+++ b/src/soc/rockchip/rk3399/include/soc/sdram.h
@@ -127,6 +127,18 @@ struct rk3399_msch_timings {
u32 agingx0;
};
+struct rk3399_ddr_cic_regs {
+ u32 cic_ctrl0;
+ u32 cic_ctrl1;
+ u32 cic_idle_th;
+ u32 cic_cg_wait_th;
+ u32 cic_status0;
+ u32 cic_status1;
+ u32 cic_ctrl2;
+ u32 cic_ctrl3;
+ u32 cic_ctrl4;
+};
+
/* DENALI_CTL_00 */
#define START (1)
diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c
index ee98033..688bdeb 100644
--- a/src/soc/rockchip/rk3399/sdram.c
+++ b/src/soc/rockchip/rk3399/sdram.c
@@ -41,6 +41,7 @@ static struct rk3399_ddr_publ_regs * const rk3399_ddr_publ[2] = {
(void *)DDRC0_PHY_BASE_ADDR, (void *)DDRC1_PHY_BASE_ADDR };
static struct rk3399_msch_regs * const rk3399_msch[2] = {
(void *)SERVER_MSCH0_BASE_ADDR, (void *)SERVER_MSCH1_BASE_ADDR };
+static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE_ADDR;
/*
* sys_reg bitfield struct
@@ -725,6 +726,7 @@ static int data_training(u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&denali_pi[175]), 0x00003f7c);
}
+ clrbits_le32(&denali_pi[100], 0x3 << 8);
}
/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
@@ -771,6 +773,7 @@ static int data_training(u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&denali_pi[175]), 0x00003f7c);
}
+ clrbits_le32(&denali_pi[60], 0x3 << 8);
}
/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
@@ -817,6 +820,7 @@ static int data_training(u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&denali_pi[175]), 0x00003f7c);
}
+ clrbits_le32(&denali_pi[80], 0x3 << 24);
}
/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
@@ -849,6 +853,7 @@ static int data_training(u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&denali_pi[175]), 0x00003f7c);
}
+ clrbits_le32(&denali_pi[80], 0x3 << 16);
}
/* wdq leveling(LPDDR4 support) */
@@ -880,6 +885,7 @@ static int data_training(u32 channel,
/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
write32((&denali_pi[175]), 0x00003f7c);
}
+ clrbits_le32(&denali_pi[124], 0x3 << 16);
}
/* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
@@ -971,6 +977,30 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params)
clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3);
}
+static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params)
+{
+ u32 channel;
+ u32 *denali_phy;
+ u32 ch_count = sdram_params->num_channels;
+
+ write32(&rk3399_ddr_cic->cic_ctrl0,
+ RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
+ 1 << 4 | 1 << 2 | 1));
+ while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2)))
+ ;
+
+ write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1));
+ while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0)))
+ ;
+
+ for (channel = 0; channel < ch_count; channel++) {
+ denali_phy = rk3399_ddr_publ[channel]->denali_phy;
+ clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
+ if (data_training(channel, sdram_params, PI_FULL_TARINING))
+ printk(BIOS_DEBUG, "training failed\n");
+ }
+}
+
void sdram_init(const struct rk3399_sdram_params *sdram_params)
{
unsigned char dramtype = sdram_params->dramtype;
@@ -1016,6 +1046,8 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params)
sdram_params->ch[channel].ddrconfig);
}
dram_all_config(sdram_params);
+ switch_to_phy_index1(sdram_params);
+
printk(BIOS_INFO, "Finish SDRAM initialization...\n");
}
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