[coreboot-gerrit] Patch merged into coreboot/master: RISCV: Clean up the common architectural code

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5965cba3dc1fc48b1a1734fc21c05950ccc7cc4f
Author: Ronald G. Minnich <rminnich at gmail.com>
Date:   Wed Oct 19 08:07:13 2016 -0700

    RISCV: Clean up the common architectural code
    
    This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload,
    entering main() with no supporting assembly code for startup. The Harvey port
    is not complete so it just panics but ... it gets started.
    
    We provide a standard payload function that takes a pointer argument
    and makes the jump from machine to supervisor mode;
    the days of kernels running in machine mode are over.
    
    We do some small tweaks to the virtual memory code. We temporarily
    disable two functions that won't work on some targets as register
    numbers changed between 1.7 and 1.9. Once lowrisc catches up
    we'll reenable them.
    
    We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual
    memory setup code.
    
    We now use the _stack and _estack from memlayout so we know where things are.
    As time goes on maybe we can kill all the magic numbers.
    
    Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9
    Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
    Reviewed-on: https://review.coreboot.org/17058
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/17058 for details.

-gerrit