[coreboot-gerrit] Patch set updated for coreboot: nb/x4x/gma.c: Remove writes to DP, FDI registers

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17111

-gerrit

commit 5061e6fd5be9eb6b08884be1914b12a0463310ad
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Mon Oct 24 17:49:35 2016 +0200

    nb/x4x/gma.c: Remove writes to DP, FDI registers
    
    Those registers are only used on more recent Intel platforms featuring a
    PCH. The DP registers on G4X hardware are at a different offset.
    
    Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/x4x/gma.c | 23 -----------------------
 1 file changed, 23 deletions(-)

diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c
index 749a7c8..62e28aa 100644
--- a/src/northbridge/intel/x4x/gma.c
+++ b/src/northbridge/intel/x4x/gma.c
@@ -74,12 +74,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
 	u32 pixel_n = 1;
 	u32 pixel_m1 = 1;
 	u32 pixel_m2 = 1;
-	u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
-	u32 data_m1;
-	u32 data_n1 = 0x00800000;
-	u32 link_m1;
-	u32 link_n1 = 0x00040000;
-
 
 	vga_gr_write(0x18, 0);
 
@@ -210,10 +204,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
 		return;
 	}
 
-	link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency;
-	data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock)
-		/ (link_frequency * 8 * 4);
-
 	printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
 	       hactive, vactive);
 	printk(BIOS_DEBUG, "Borders %d x %d\n",
@@ -228,12 +218,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
 			    ? "Spread spectrum clock\n" : "DREF clock\n"));
 	printk(BIOS_DEBUG, "Polarities %d, %d\n",
 	       hpolarity, vpolarity);
-	printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
-	       data_m1, data_n1);
-	printk(BIOS_DEBUG, "Link frequency %d kHz\n",
-	       link_frequency);
-	printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n",
-	       link_m1, link_n1);
 	printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n",
 		pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2);
 	printk(BIOS_DEBUG, "Pixel clock %d kHz\n",
@@ -305,13 +289,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info,
 	}
 
 	mdelay(1);
-
-	write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1);
-	write32(mmio + PIPE_DATA_N1(0), data_n1);
-	write32(mmio + PIPE_LINK_M1(0), link_m1);
-	write32(mmio + PIPE_LINK_N1(0), link_n1);
-
-	mdelay(1);
 	write32(mmio + PIPECONF(0), PIPECONF_BPP_6);
 	write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN);
 	write32(mmio + PIPECONF(0), PIPECONF_ENABLE