[coreboot-gerrit] New patch to review for coreboot: driver/intel/fsp2_0: Reset on invalid stage cache.

[Naresh Solanki (naresh.solanki@intel.com)]

Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17112

-gerrit

commit b6b5bb346710b17aa55a90d370f046f2e5c88c14
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Mon Oct 24 13:01:28 2016 +0530

    driver/intel/fsp2_0: Reset on invalid stage cache.
    
    Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is invalid
    during S3 resume.
    
    Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/drivers/intel/fsp1_1/Kconfig       | 4 ++++
 src/drivers/intel/fsp2_0/Kconfig       | 4 ++++
 src/drivers/intel/fsp2_0/stage_cache.c | 9 +++++++++
 3 files changed, 17 insertions(+)

diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig
index 306e09b..cc3c0a7 100644
--- a/src/drivers/intel/fsp1_1/Kconfig
+++ b/src/drivers/intel/fsp1_1/Kconfig
@@ -111,4 +111,8 @@ config CHECKLIST_DATA_FILE_LOCATION
 	string
 	default "src/vendorcode/intel/fsp/fsp1_1/checklist"
 
+config RESET_ON_INVALID_RAMSTAGE_CACHE
+	bool "Reset the system on S3 wake when ramstage cache invalid."
+	default n
+
 endif #PLATFORM_USES_FSP1_1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 3ffb402..c653148 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -90,4 +90,8 @@ config CHECKLIST_DATA_FILE_LOCATION
 	string
 	default "src/vendorcode/intel/fsp/fsp2_0/checklist"
 
+config RESET_ON_INVALID_RAMSTAGE_CACHE
+	bool "Reset the system on S3 wake when ramstage cache invalid."
+	default n
+
 endif
diff --git a/src/drivers/intel/fsp2_0/stage_cache.c b/src/drivers/intel/fsp2_0/stage_cache.c
index 2d594e6..4469a7f 100644
--- a/src/drivers/intel/fsp2_0/stage_cache.c
+++ b/src/drivers/intel/fsp2_0/stage_cache.c
@@ -17,6 +17,8 @@
 #include <console/console.h>
 #include <fsp/memmap.h>
 #include <stage_cache.h>
+#include <reset.h>
+#include <program_loading.h>
 
 void stage_cache_external_region(void **base, size_t *size)
 {
@@ -26,3 +28,10 @@ void stage_cache_external_region(void **base, size_t *size)
 		*size = 0;
 	}
 }
+
+void ramstage_cache_invalid(void)
+{
+	if (IS_ENABLED(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE))
+		/* Perform cold reset on invalid ramstage cache. */
+		hard_reset();
+}