[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/common: Enable support to write protect SPI flash range
gerrit at coreboot.org
gerrit at coreboot.org
Wed Oct 26 01:50:40 CEST 2016
the following patch was just integrated into master:
commit aedbfc8f0917b332e648fe6c4333567bd8e58b0d
Author: Furquan Shaikh <furquan at chromium.org>
Date: Mon Oct 24 15:23:40 2016 -0700
soc/intel/common: Enable support to write protect SPI flash range
Write-protect SPI flash range provided by caller by using a free Flash
Protected Range (FPR) register. This expects SoC to define a callback
for providing information about the first FPR register address and
maximum number of FPRs supported.
BUG=chrome-os-partner:58896
Change-Id: I4e34ede8784e5587a5e08ffa10e20d2d14e20add
Signed-off-by: Furquan Shaikh <furquan at chromium.org>
Reviewed-on: https://review.coreboot.org/17115
Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/17115 for details.
-gerrit
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