[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/apollolake: Enable write-protect SPI flash range support

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit ffb3a2d22506a86e205a757029f60abccfef0486
Author: Furquan Shaikh <furquan at chromium.org>
Date:   Mon Oct 24 15:28:23 2016 -0700

    soc/intel/apollolake: Enable write-protect SPI flash range support
    
    Use intel common infrastructure to enable support for write-protecting
    SPI flash range. Also, enable this protection for RW_MRC_CACHE.
    
    BUG=chrome-os-partner:58896
    TEST=Verified that write to RW_MRC_CACHE fails in OS using
    "flashrom -p host -i RW_MRC_CACHE -w /tmp/test.bin"
    
    Change-Id: I35df12bc295d141e314ec2cb092d904842432394
    Signed-off-by: Furquan Shaikh <furquan at chromium.org>
    Reviewed-on: https://review.coreboot.org/17117
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)


See https://review.coreboot.org/17117 for details.

-gerrit