[coreboot-gerrit] New patch to review for coreboot: skylake: Support for early I2C TPM driver

Duncan Laurie (dlaurie@chromium.org) gerrit at coreboot.org
Wed Oct 26 05:11:07 CEST 2016


Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17136

-gerrit

commit 7c60288ab7eb9fdff70bb247897c36253145338d
Author: Duncan Laurie <dlaurie at chromium.org>
Date:   Tue Oct 25 20:05:31 2016 -0700

    skylake: Support for early I2C TPM driver
    
    Add the SOC definition for acpi_get_gpe() so it can be used
    by the I2C TPM driver.  Also add the I2C support code to
    verstage so it can get used by vboot.
    
    BUG=chrome-os-partner:58666
    TEST=boot with I2C TPM on skylake board
    
    Change-Id: I553f00a6ec25955ecc18a7616d9c3e1e7cbbb8ca
    Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
 src/soc/intel/skylake/Makefile.inc |  1 +
 src/soc/intel/skylake/pmutil.c     | 20 ++++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index d7f772d..b06c85b 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -31,6 +31,7 @@ verstage-y += flash_controller.c
 verstage-y += monotonic_timer.c
 verstage-y += pch.c
 verstage-y += pmutil.c
+verstage-y += bootblock/i2c.c
 verstage-$(CONFIG_UART_DEBUG) += uart_debug.c
 
 romstage-y += flash_controller.c
diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c
index 6ead7ed..203a430 100644
--- a/src/soc/intel/skylake/pmutil.c
+++ b/src/soc/intel/skylake/pmutil.c
@@ -356,6 +356,26 @@ u32 clear_gpe_status(void)
 				gpe0_sts_3_bits);
 }
 
+/* Read and clear GPE status (defined in arch/acpi.h) */
+int acpi_get_gpe(int gpe)
+{
+	int bank;
+	uint32_t mask, sts;
+
+	if (gpe < 0 || gpe > GPE0_WADT)
+		return -1;
+
+	bank = gpe / 32;
+	mask = 1 << (gpe % 32);
+
+	sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank));
+	if (sts & mask) {
+		outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank));
+		return 1;
+	}
+	return 0;
+}
+
 /* Enable all requested GPE */
 void enable_all_gpe(u32 set1, u32 set2, u32 set3, u32 set4)
 {



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