[coreboot-gerrit] Patch merged into coreboot/master: intel/skylake: Add support to enable wake-on-usb attach/detach

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 3bfe3404df32ca226c624be0435c640bf1ebeae7
Author: Furquan Shaikh <furquan at chromium.org>
Date:   Tue Oct 18 14:25:25 2016 -0700

    intel/skylake: Add support to enable wake-on-usb attach/detach
    
    Three things are required to enable wake-on-usb:
    1. 5V to USB ports should be enabled in S3.
    2. ASL file needs to have appropriate wake bit set.
    3. XHCI controller should have the wake on attach/detach bit set for the
    corresponding port in PORTSCN register.
    
    Only part missing was #3.
    
    This CL adds support to allow mainboard to define a bitmap in
    devicetree corresponding to the ports that it wants to enable
    wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in
    PORTSCN would be set by xhci.asl for the appropriate ports.
    
    BUG=chrome-os-partner:58734
    BRANCH=None
    TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb
    attach/detach.
    
    Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf
    Signed-off-by: Furquan Shaikh <furquan at chromium.org>
    Reviewed-on: https://review.coreboot.org/17056
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/17056 for details.

-gerrit