[coreboot-gerrit] Patch set updated for coreboot: nb/intel/gm45: Use LAPIC udelay instead of custom version

[Arthur Heymans (arthur@aheymans.xyz)]

Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17152

-gerrit

commit 3875a3716965de11ed3a2d540d477daac0cf34fa
Author: Arthur Heymans <arthur at aheymans.xyz>
Date:   Thu Oct 27 00:31:41 2016 +0200

    nb/intel/gm45: Use LAPIC udelay instead of custom version
    
    This change may slow down the raminit by maximum 200usec,
    but reuses the lapic udelay definition.
    
    Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed
    Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
 src/northbridge/intel/gm45/Kconfig      |  2 +-
 src/northbridge/intel/gm45/Makefile.inc |  1 -
 src/northbridge/intel/gm45/delay.c      | 10 ----------
 src/northbridge/intel/gm45/delay.h      | 24 ------------------------
 src/northbridge/intel/gm45/raminit.c    |  8 ++++----
 5 files changed, 5 insertions(+), 40 deletions(-)

diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index d254b9e..d4f4390 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy
 	select VGA
 	select INTEL_EDID
 	select INTEL_GMA_ACPI
-	select UDELAY_TSC
+	select UDELAY_LAPIC
 
 config CBFS_SIZE
 	hex
diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc
index 794b2b9..ac5810b 100644
--- a/src/northbridge/intel/gm45/Makefile.inc
+++ b/src/northbridge/intel/gm45/Makefile.inc
@@ -17,7 +17,6 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_GM45),y)
 
 romstage-y += early_init.c
 romstage-y += early_reset.c
-romstage-y += delay.c
 romstage-y += raminit.c
 romstage-y += raminit_rcomp_calibration.c
 romstage-y += raminit_receive_enable_calibration.c
diff --git a/src/northbridge/intel/gm45/delay.c b/src/northbridge/intel/gm45/delay.c
index ad2e543..328c751 100644
--- a/src/northbridge/intel/gm45/delay.c
+++ b/src/northbridge/intel/gm45/delay.c
@@ -84,13 +84,3 @@ void udelay(const u32 us)
 {
 	_udelay(us, 1, 0);
 }
-
-void ns100delay(const u32 ns100)
-{
-	_udelay(ns100, 10, 0);
-}
-
-void udelay_from_reset(const u32 us)
-{
-	_udelay(us, 1, 1);
-}
diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h
deleted file mode 100644
index d84c5fb..0000000
--- a/src/northbridge/intel/gm45/delay.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 secunet Security Networks AG
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__
-#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__
-
-#include <delay.h>
-
-void ns100delay(u32);
-void udelay_from_reset(u32);
-
-#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 37b44cc..167ef24 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -24,7 +24,7 @@
 #include <spd.h>
 #include <console/console.h>
 #include <lib.h>
-#include "delay.h"
+#include <delay.h>
 #include "gm45.h"
 #include "chip.h"
 
@@ -916,15 +916,15 @@ static void rcomp_initialization(const stepping_t stepping, const int sff)
 
 static void dram_powerup(const int resume)
 {
-	udelay_from_reset(200);
+	udelay(200);
 	MCHBAR32(CLKCFG_MCHBAR) = (MCHBAR32(CLKCFG_MCHBAR) & ~(1 << 3)) | (3 << 21);
 	if (!resume) {
 		MCHBAR32(0x1434) |= (1 << 10);
-		ns100delay(2);
+		udelay(1);
 	}
 	MCHBAR32(0x1434) |= (1 << 6);
 	if (!resume) {
-		ns100delay(1);
+		udelay(1);
 		MCHBAR32(0x1434) |= (1 << 9);
 		MCHBAR32(0x1434) &= ~(1 << 10);
 		udelay(500);