[coreboot-gerrit] Patch merged into coreboot/master: driver/intel/fsp2_0: Reset on invalid stage cache.

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit d5353e36483daef462fd37e47aa4c0524f868ace
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Mon Oct 24 13:01:28 2016 +0530

    driver/intel/fsp2_0: Reset on invalid stage cache.
    
    Add config in fsp 2.0/1.1 driver to reset if ramstage stage cache is
    invalid during S3 resume.
    
    Change-Id: I83fe76957c061f20e9afb308e55923806fda4f93
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
    Reviewed-on: https://review.coreboot.org/17112
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>
    Tested-by: build bot (Jenkins)
    Reviewed-by: Furquan Shaikh <furquan at google.com>


See https://review.coreboot.org/17112 for details.

-gerrit