[coreboot-gerrit] Patch set updated for coreboot: mb/gigabyte/ga-945gcm-s2l: add mainboard
Arthur Heymans (arthur@aheymans.xyz)
gerrit at coreboot.org
Thu Oct 27 21:23:15 CEST 2016
Arthur Heymans (arthur at aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17033
-gerrit
commit b0d59c909677ebce6219ea038ee8d84fe3b94a8b
Author: Arthur Heymans <arthur at aheymans.xyz>
Date: Sat Oct 15 18:00:22 2016 +0200
mb/gigabyte/ga-945gcm-s2l: add mainboard
Startpoint was Intel d945gclf, which has same chipset and
Gigabyte ga-g41m-es2l which has same Superio.
What works and is tested:
* PCI slot;
* PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card;
* onboard VGA output (only textmode implemented) with native graphic init;
* 533, 800, 1067MHz CPU (1333MHz is unsupported by the chipset);
* serial output during and after boot.
What does not work:
* resume from suspend (does not work for d945gclf either).
Quirks:
* The Realtek ethernet card requires a reset which currently also
hardcodes a MAC adress.
This board was only tested with the SeaBIOS payload due to flash size
constraints (512KB) and with GNU/Linux.
Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig | 58 ++++++
src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name | 2 +
src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc | 1 +
src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl | 51 +++++
.../gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl | 75 +++++++
.../gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl | 44 +++++
.../gigabyte/ga-945gcm-s2l/acpi/mainboard.asl | 30 +++
.../gigabyte/ga-945gcm-s2l/acpi/platform.asl | 48 +++++
.../gigabyte/ga-945gcm-s2l/acpi/superio.asl | 1 +
.../gigabyte/ga-945gcm-s2l/acpi/thermal.asl | 1 +
src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c | 32 +++
.../gigabyte/ga-945gcm-s2l/board_info.txt | 6 +
src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default | 7 +
src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout | 122 ++++++++++++
src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c | 20 ++
src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 160 +++++++++++++++
src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl | 53 +++++
src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c | 37 ++++
src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 217 +++++++++++++++++++++
19 files changed, 965 insertions(+)
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
new file mode 100644
index 0000000..b41becc
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig
@@ -0,0 +1,58 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans <arthur at ahemans.xyz
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+if BOARD_GIGABYTE_GA_945GCM_S2L
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select ARCH_X86
+ select CPU_INTEL_SOCKET_LGA775
+ select NORTHBRIDGE_INTEL_I945
+ select NORTHBRIDGE_INTEL_SUBTYPE_I945GC
+ select CHECK_SLFRCS_ON_RESUME
+ select SOUTHBRIDGE_INTEL_I82801GX
+ select SUPERIO_ITE_IT8718F
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select HAVE_MP_TABLE
+ select HAVE_ACPI_TABLES
+ select HAVE_ACPI_RESUME
+ select BOARD_ROMSIZE_KB_512
+ select CHANNEL_XOR_RANDOMIZATION
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_EDID
+ select REALTEK_8168_RESET
+
+config MAINBOARD_DIR
+ string
+ default gigabyte/ga-945gcm-s2l
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "GA-945GCM-S2L"
+
+config MMCONF_BASE_ADDRESS
+ hex
+ default 0xf0000000
+
+config IRQ_SLOT_COUNT
+ int
+ default 18
+
+config MAX_CPUS
+ int
+ default 2
+
+endif # BOARD_GIGABYTE_GA_945GCM_S2L
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name
new file mode 100644
index 0000000..95baebe
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GIGABYTE_GA_945GCM_S2L
+ bool "GA-945GCM-S2L"
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc
new file mode 100644
index 0000000..f9621db
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc
@@ -0,0 +1 @@
+ramstage-y += cstates.c
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl
new file mode 100644
index 0000000..5362bb2
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ec.asl
@@ -0,0 +1,51 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device(EC0)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 1)
+
+ // _REG method requires that an operation region be defined.
+ OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+ Field (ERAM, ByteAcc, Lock, Preserve)
+ {
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (ECMD, ResourceTemplate()
+ {
+ IO (Decode16, 0x62, 0x62, 0, 1)
+ IO (Decode16, 0x66, 0x66, 0, 1)
+ })
+
+ Return (ECMD)
+ }
+
+ Method (_REG, 2)
+ {
+ // This method is needed by Windows XP/2000
+ // for EC initialization before a driver
+ // is loaded
+ }
+
+ Name (_GPE, 23) // GPI07 / GPE23 -> Runtime SCI
+
+ // TODO EC Query methods
+
+ // TODO Scope _SB devices for AC power, LID, Power button
+
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl
new file mode 100644
index 0000000..4aaa33f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * i945
+ */
+
+
+// PCI Interrupt Routing
+Method(_PRT)
+{
+ If (PICM) {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, 0, 16 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, 0, 16 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, 0, 16 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, 0, 16 },
+ Package() { 0x001cffff, 1, 0, 17 },
+ Package() { 0x001cffff, 2, 0, 18 },
+ Package() { 0x001cffff, 3, 0, 19 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, 0, 16 },
+ Package() { 0x001dffff, 1, 0, 17 },
+ Package() { 0x001dffff, 2, 0, 18 },
+ Package() { 0x001dffff, 3, 0, 19 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, 0, 16 },
+ Package() { 0x001fffff, 1, 0, 17 },
+ Package() { 0x001fffff, 2, 0, 18 },
+ Package() { 0x001fffff, 3, 0, 19 },
+
+ })
+
+ } Else {
+ Return (Package() {
+ // PCIe Graphics 0:1.0
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // Onboard graphics (IGD) 0:2.0
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // High Definition Audio 0:1b.0
+ Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ // PCIe Root Ports 0:1c.x
+ Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // USB and EHCI 0:1d.x
+ Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ // LPC device 0:1f.0
+ Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
+ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 },
+ Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
+ Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
+ })
+ }
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl
new file mode 100644
index 0000000..cc229a5
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/ich7_pci_irqs.asl
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* This is board specific information: IRQ routing for the
+ * 0:1e.0 PCI bridge of the ICH7
+ */
+
+
+If (PICM) {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x14 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x13 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x13 },
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x10 },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x14 },
+
+ })
+} Else {
+ Return (Package() {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LPCB.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LPCB.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LPCB.LNKA, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LPCB.LNKE, 0x00 },
+ })
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl
new file mode 100644
index 0000000..0454c3f
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/mainboard.asl
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Device (SLPB)
+{
+ Name(_HID, EisaId("PNP0C0E"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+
+ // Wake
+ Name(_PRW, Package(){0x1d, 0x04})
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl
new file mode 100644
index 0000000..21eb3df
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/platform.asl
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* The _PTS method (Prepare To Sleep) is called before the OS is
+ * entering a sleep state. The sleep state number is passed in Arg0
+ */
+
+Method(_PTS,1)
+{
+ // Call a trap so SMI can prepare for Sleep as well.
+ // TRAP(0x55)
+}
+
+/* The _WAK method is called on system wakeup */
+
+Method(_WAK,1)
+{
+ // CPU specific part
+
+ // Notify PCI Express slots in case a card
+ // was inserted while a sleep state was active.
+
+ // Are we going to S3?
+ If (LEqual(Arg0, 3)) {
+ // ..
+ }
+
+ // Are we going to S4?
+ If (LEqual(Arg0, 4)) {
+ // ..
+ }
+
+ // TODO: Windows XP SP2 P-State restore
+
+ Return(Package(){0,0})
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl
new file mode 100644
index 0000000..4107d3b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/superio.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl
new file mode 100644
index 0000000..4107d3b
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi/thermal.asl
@@ -0,0 +1 @@
+/* dummy */
\ No newline at end of file
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c
new file mode 100644
index 0000000..677ebcf
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/acpi_tables.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <arch/ioapic.h>
+
+#include "southbridge/intel/i82801gx/nvs.h"
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/board_info.txt b/src/mainboard/gigabyte/ga-945gcm-s2l/board_info.txt
new file mode 100644
index 0000000..70cbe41
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: http://www.gigabyte.com/products/product-page.aspx?pid=2669#ov
+Release year: 2007
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default
new file mode 100644
index 0000000..ab7aac1
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+baud_rate=115200
+debug_level=Spew
+hyper_threading=Enable
+nmi=Enable
+boot_devices=''
+gfx_uma_size=8M
\ No newline at end of file
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout
new file mode 100644
index 0000000..47f48dd
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout
@@ -0,0 +1,122 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+# Status Register A
+# -----------------------------------------------------------------
+# Status Register B
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+
+# coreboot config options: northbridge
+411 3 e 11 gfx_uma_size
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 80 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# RAM initialization internal data
+1024 8 r 0 C0WL0REOST
+1032 8 r 0 C1WL0REOST
+1040 8 r 0 RCVENMT
+1048 4 r 0 C0DRT1
+1052 4 r 0 C1DRT1
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+11 0 1M
+11 1 4M
+11 2 8M
+11 3 16M
+11 4 32M
+11 5 48M
+11 6 64M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c
new file mode 100644
index 0000000..f683756
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cstates.c
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <arch/x86/include/arch/acpigen.h>
+
+int get_cst_entries(acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
new file mode 100644
index 0000000..a993848
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb
@@ -0,0 +1,160 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2009 coresystems GmbH
+## Copyright (C) 2016 Arthur Heymans arthur at aheymans.xyz
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip northbridge/intel/i945
+
+ device cpu_cluster 0 on
+ chip cpu/intel/socket_LGA775
+ device lapic 0 on end
+ end
+ chip cpu/intel/model_1067x
+ device lapic 0xACAC off end
+ end
+ end
+
+ device domain 0 on
+ device pci 00.0 on # host bridge
+ subsystemid 0x1458 0x5000
+ end
+ device pci 01.0 on # i945 PCIe root port
+ subsystemid 0x1458 0x5000
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 02.0 on # vga controller
+ subsystemid 0x1458 0xd000
+ ioapic_irq 2 INTA 0x10
+ end
+
+ chip southbridge/intel/i82801gx
+ register "pirqa_routing" = "0x8c"
+ register "pirqb_routing" = "0x8a"
+ register "pirqc_routing" = "0x83"
+ register "pirqd_routing" = "0x8b"
+ register "pirqe_routing" = "0x80"
+ register "pirqf_routing" = "0x80"
+ register "pirqg_routing" = "0x80"
+ register "pirqh_routing" = "0x85"
+
+ # GPI routing
+ # 0 No effect (default)
+ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ # 2 SCI (if corresponding GPIO_EN bit is also set)
+ register "gpi0_routing" = "1"
+ register "gpi1_routing" = "1"
+ register "gpi2_routing" = "1"
+ register "gpi3_routing" = "1"
+ register "gpi4_routing" = "1"
+ register "gpi5_routing" = "1"
+ register "gpi6_routing" = "1"
+ register "gpi7_routing" = "1"
+ register "gpi8_routing" = "1"
+ register "gpi9_routing" = "1"
+ register "gpi10_routing" = "1"
+ register "gpi11_routing" = "1"
+ register "gpi12_routing" = "1"
+ register "gpi13_routing" = "2"
+ register "gpi14_routing" = "1"
+ register "gpi15_routing" = "1"
+
+ register "gpe0_en" = "0"
+
+ register "ide_legacy_combined" = "0x0"
+ register "ide_enable_primary" = "0x1"
+ register "ide_enable_secondary" = "0x0"
+ register "sata_ahci" = "0x0"
+ register "c3_latency" = "85"
+
+ register "p_cnt_throttling_supported" = "0"
+
+ device pci 1b.0 on # High Definition Audio
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1c.0 on end # PCIe
+ device pci 1c.1 on end # PCIe
+ #device pci 1c.2 off end # PCIe port 3
+ #device pci 1c.3 off end # PCIe port 4
+ #device pci 1c.4 off end # PCIe port 5
+ #device pci 1c.5 off end # PCIe port 6
+ device pci 1d.0 on # USB UHCI
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1d.1 on # USB UHCI
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1d.2 on # USB UHCI
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1d.3 on # USB UHCI
+ ioapic_irq 2 INTD 0x13
+ end
+ device pci 1d.7 on # USB2 EHCI
+ ioapic_irq 2 INTA 0x10
+ end
+ device pci 1e.0 on end # PCI bridge
+
+ device pci 1f.0 on # LPC bridge
+ ioapic_irq 2 INTA 0x10
+ chip superio/ite/it8718f # Super I/O
+ device pnp 2e.0 off end # Floppy
+ device pnp 2e.1 on # COM1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.2 off end # COM2
+ device pnp 2e.3 on # Parallel port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ io 0x62 = 0
+ drq 0x74 = 4
+ irq 0xf0 = 0x08
+ end
+ device pnp 2e.4 on # Environment controller
+ io 0x60 = 0x290
+ irq 0x70 = 0x00
+ io 0x62 = 0x000
+ irq 0xf0 = 0x00
+ irq 0xf1 = 0x00
+ irq 0xf2 = 0x0a
+ irq 0xf3 = 0x00
+ irq 0xf4 = 0x80
+ irq 0xf5 = 0x20
+ irq 0xf6 = 0x3e
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ irq 0x70 = 1
+ io 0x62 = 0x64
+ irq 0xf0 = 0x48
+ end
+ device pnp 2e.6 on # Mouse
+ irq 0x70 = 0
+ irq 0x71 = 2
+ irq 0xf0 = 0
+ end
+ end
+ end
+ device pci 1f.1 on # IDE
+ ioapic_irq 2 INTB 0x11
+ end
+ device pci 1f.2 on # SATA
+ ioapic_irq 2 INTC 0x12
+ end
+ device pci 1f.3 on # SMBus
+ ioapic_irq 2 INTD 0x13
+ end
+ end
+ end
+end
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl
new file mode 100644
index 0000000..187481a
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20090419 // OEM revision
+)
+{
+ // Some generic macros
+ #include "acpi/platform.asl"
+
+ // global NVS and variables
+ #include <southbridge/intel/i82801gx/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ // General Purpose Events
+ //#include "acpi/gpe.asl"
+
+ // mainboard specific devices
+ #include "acpi/mainboard.asl"
+
+ // Thermal Zone
+ //#include "acpi/thermal.asl"
+
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <northbridge/intel/i945/acpi/i945.asl>
+ #include <southbridge/intel/i82801gx/acpi/ich7.asl>
+ }
+ }
+
+ /* Chipset specific sleep states */
+ #include <southbridge/intel/i82801gx/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c
new file mode 100644
index 0000000..1b57dfa
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/hda_verb.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Arthur Heymans <arthur at aheymans.xyz>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x10ec0662, /* Vendor ID */
+ 0x1458a002, /* Subsystem ID */
+ 0x00000009, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x15, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a19830),
+ AZALIA_PIN_CFG(0, 0x19, 0x02a19c31),
+ AZALIA_PIN_CFG(0, 0x1a, 0x0181303f),
+ AZALIA_PIN_CFG(0, 0x1b, 0x02214c1f),
+ AZALIA_PIN_CFG(0, 0x1c, 0x593301f0),
+ AZALIA_PIN_CFG(0, 0x1d, 0x4005c603),
+ AZALIA_PIN_CFG(0, 0x1e, 0x014b6120),
+};
+
+const u32 pc_beep_verbs[0] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
new file mode 100644
index 0000000..2965ff4
--- /dev/null
+++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c
@@ -0,0 +1,217 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2016 Arthur Heymans arthur at aheymans.xyz
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// __PRE_RAM__ means: use "unsigned" for device, not a struct.
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+#include <lib.h>
+#include <arch/acpi.h>
+#include <cbmem.h>
+#include <superio/ite/it8718f/it8718f.h>
+#include <superio/ite/common/ite.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
+#include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
+
+#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1)
+#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO)
+#define EC_DEV PNP_DEV(0x2e, IT8718F_EC)
+#define SUPERIO_DEV PNP_DEV(0x2e, 0)
+
+void setup_ich7_gpios(void)
+{
+ /* TODO: This is highly board specific and should be moved */
+ printk(BIOS_DEBUG, " GPIOS...");
+ /* General Registers */
+ outl(0x1f15f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */
+ outl(0xe0e8ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */
+ outl(0xe2fefc03, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */
+ /* Output Control Registers */
+ outl(0x00400000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */
+ /* Input Control Registers */
+ outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */
+ outl(0x000000c7, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */
+ outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */
+ outl(0x000000f2, DEFAULT_GPIOBASE + 0x38); /* GP_LVL2 */
+}
+
+static void setup_sio(void)
+{
+ /* Set default GPIOs on superio */
+ ite_reg_write(GPIO_DEV, 0x25, 0x40);
+ ite_reg_write(GPIO_DEV, 0x26, 0x3f);
+ ite_reg_write(GPIO_DEV, 0x28, 0x41);
+ ite_reg_write(GPIO_DEV, 0x29, 0x88);
+ ite_reg_write(GPIO_DEV, 0x2c, 0x1c);
+ ite_reg_write(GPIO_DEV, 0x62, 0x08);
+ ite_reg_write(GPIO_DEV, 0x72, 0x00);
+ ite_reg_write(GPIO_DEV, 0x73, 0x38);
+ ite_reg_write(GPIO_DEV, 0xb1, 0x01);
+ ite_reg_write(GPIO_DEV, 0xb8, 0x80);
+ ite_reg_write(GPIO_DEV, 0xbb, 0x40);
+ ite_reg_write(GPIO_DEV, 0xc0, 0x00);
+ ite_reg_write(GPIO_DEV, 0xc3, 0x00);
+ ite_reg_write(GPIO_DEV, 0xc8, 0x00);
+ ite_reg_write(GPIO_DEV, 0xcb, 0x00);
+ ite_reg_write(GPIO_DEV, 0xf6, 0x26);
+ ite_reg_write(GPIO_DEV, 0xfc, 0x4a);
+
+ ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9
+ ite_reg_write(EC_DEV, 0x30, 0xff); // Enable
+}
+
+static void ich7_enable_lpc(void)
+{
+ // Enable Serial IRQ
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0);
+ // Set COM1/COM2 decode range
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ // Enable COM1
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340d);
+ // Enable SuperIO Power Management Events
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0801);
+}
+
+static void rcba_config(void)
+{
+ /* Enable IOAPIC */
+ RCBA8(0x31ff) = 0x03;
+
+ /* Disable unused devices */
+ RCBA32(0x3418) = 0x003c0061;
+
+ /* Enable PCIe Root Port Clock Gate */
+ RCBA32(0x341c) = 0x00000001;
+}
+
+static void early_ich7_init(void)
+{
+ uint8_t reg8;
+ uint32_t reg32;
+
+ // program secondary mlt XXX byte?
+ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20);
+
+ // reset rtc power status
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+ reg8 &= ~(1 << 2);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8);
+
+ // usb transient disconnect
+ reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad);
+ reg8 |= (3 << 0);
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc);
+ reg32 |= (1 << 29) | (1 << 17);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32);
+
+ reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc);
+ reg32 |= (1 << 31) | (1 << 27);
+ pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32);
+
+ RCBA32(0x0088) = 0x0011d000;
+ RCBA16(0x01fc) = 0x060f;
+ RCBA32(0x01f4) = 0x86000040;
+ RCBA32(0x0214) = 0x10030509;
+ RCBA32(0x0218) = 0x00020504;
+ RCBA8(0x0220) = 0xc5;
+ reg32 = RCBA32(0x3410);
+ reg32 |= (1 << 6);
+ RCBA32(0x3410) = reg32;
+ reg32 = RCBA32(0x3430);
+ reg32 &= ~(3 << 0);
+ reg32 |= (1 << 0);
+ RCBA32(0x3430) = reg32;
+ RCBA32(0x3418) |= (1 << 0);
+ RCBA16(0x0200) = 0x2008;
+ RCBA8(0x2027) = 0x0d;
+ RCBA16(0x3e08) |= (1 << 7);
+ RCBA16(0x3e48) |= (1 << 7);
+ RCBA32(0x3e0e) |= (1 << 7);
+ RCBA32(0x3e4e) |= (1 << 7);
+
+ // next step only on ich7m b0 and later:
+ reg32 = RCBA32(0x2034);
+ reg32 &= ~(0x0f << 16);
+ reg32 |= (5 << 16);
+ RCBA32(0x2034) = reg32;
+}
+
+void mainboard_romstage_entry(unsigned long bist)
+{
+ int s3resume = 0, boot_mode = 0;
+
+ if (bist == 0)
+ enable_lapic();
+
+ ich7_enable_lpc();
+ /* Enable SuperIO PM */
+ setup_sio();
+ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ /* Disable SIO reboot */
+ ite_reg_write(GPIO_DEV, 0xEF, 0x7E);
+
+ /* Set up the console */
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ if (MCHBAR16(SSKPD) == 0xCAFE) {
+ printk(BIOS_DEBUG, "soft reset detected.\n");
+ boot_mode = 1;
+ }
+
+ /* Perform some early chipset initialization required
+ * before RAM initialization can work
+ */
+ i945_early_initialization();
+
+ s3resume = southbridge_detect_s3_resume();
+
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+
+#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8
+ dump_spd_registers();
+#endif
+ sdram_initialize(s3resume ? 2 : boot_mode, NULL);
+
+ /* Perform some initialization that must run before stage2 */
+ early_ich7_init();
+
+ /* This should probably go away. Until now it is required
+ * and mainboard specific
+ */
+ rcba_config();
+
+ /* Chipset Errata! */
+ fixup_i945_errata();
+
+ /* Initialize the internal PCIe links before we go into stage2 */
+ i945_late_initialization(s3resume);
+}
More information about the coreboot-gerrit
mailing list