[coreboot-gerrit] New patch to review for coreboot: skylake: Add GPIO macro for confuring inverted APIC input
Duncan Laurie (dlaurie@chromium.org)
gerrit at coreboot.org
Fri Oct 28 18:16:58 CEST 2016
Duncan Laurie (dlaurie at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17176
-gerrit
commit 79328231c752d370fff432ba3e1dc67f04b9e68d
Author: Duncan Laurie <dlaurie at chromium.org>
Date: Fri Oct 28 09:07:49 2016 -0700
skylake: Add GPIO macro for confuring inverted APIC input
Add a GPIO macro that allows a pin to be routed to the APIC with
the input inverted. This allows a normal interrupt to get used as
a GPE during firmware and still be used as a perhiperal interrupt
in the kernel.
BUG=chrome-os-partner:58666
TEST=boot en eve and use TPM IRQ in firmware and OS
Change-Id: I77f727f749fdd5281ff595a9237fe1e634daba96
Signed-off-by: Duncan Laurie <dlaurie at chromium.org>
---
src/soc/intel/skylake/include/soc/gpio.h | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h
index d86af0f..c520af7 100644
--- a/src/soc/intel/skylake/include/soc/gpio.h
+++ b/src/soc/intel/skylake/include/soc/gpio.h
@@ -144,6 +144,11 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num);
_PAD_CFG(pad_, term_, \
_DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, YES, NO, NO, NO, GPIO, NO, YES))
+/* General purpose input passed through to IOxAPIC as inverted input. */
+#define PAD_CFG_GPI_APIC_INVERT(pad_, term_, rst_) \
+ _PAD_CFG(pad_, term_, \
+ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, YES, YES, NO, NO, NO, GPIO, NO, YES))
+
/* General purpose input routed to SCI. This assumes edge triggered events. */
#define PAD_CFG_GPI_ACPI_SCI(pad_, term_, rst_, inv_) \
_PAD_CFG_ATTRS(pad_, term_, \
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