[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: don't hardcode GPE0 standard reg

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 64606cea9394bf3b3a3803450f6e31c75800193c
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Thu Oct 27 09:53:17 2016 -0500

    soc/intel/skylake: don't hardcode GPE0 standard reg
    
    While using '3' is fine for the standard gpe0 for skylake, I want
    to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX
    without the hard coded index. If that does happen now things will
    still work, but it may just not match the hardware proper.
    
    BUG=chrome-os-partner:58666
    
    Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
    Reviewed-on: https://review.coreboot.org/17160
    Tested-by: build bot (Jenkins)
    Reviewed-by: Paul Menzel <paulepanter at users.sourceforge.net>
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>


See https://review.coreboot.org/17160 for details.

-gerrit