[coreboot-gerrit] Patch set updated for coreboot: mainboard/intel/kblrvp: Update onboard memory specific configs

[Naresh Solanki (naresh.solanki@intel.com)]

Naresh Solanki (naresh.solanki at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17162

-gerrit

commit 9dc32da05865f102b369d37e245a0b065c87b067
Author: Naresh G Solanki <naresh.solanki at intel.com>
Date:   Thu Oct 27 21:18:25 2016 +0530

    mainboard/intel/kblrvp: Update onboard memory specific configs
    
    1. Update dq, dqs map & Rcomp strength & Rcomp target.
    2. Fix rvp3.spd.hex byte 2 to 0x1F(LPDDR3 memory type).
    
    Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
---
 src/mainboard/intel/kblrvp/spd/rvp3.spd.hex |  4 ++--
 src/mainboard/intel/kblrvp/spd/spd_util.c   | 20 +++++---------------
 2 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
index e032411..9be3298 100644
--- a/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
+++ b/src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
@@ -1,4 +1,4 @@
-24 20 F1 0E 14 11 95 00 00 00 00 03 0B 23 00 00
+24 20 0F 0E 14 11 95 00 00 00 00 03 0B 23 00 00
 00 00 0A FF 54 00 00 00 78 00 90 A8 90 10 04 E0
 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
@@ -13,4 +13,4 @@
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
-00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
\ No newline at end of file
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c
index f29f1e33..cc88301 100644
--- a/src/mainboard/intel/kblrvp/spd/spd_util.c
+++ b/src/mainboard/intel/kblrvp/spd/spd_util.c
@@ -28,8 +28,8 @@ void mainboard_fill_dq_map_data(void *dq_map_ptr)
 	const u8 dq_map[2][12] = {
 		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
 		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
-		  { 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
-		    0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
+		  { 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
+		    0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
 	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
 }
 
@@ -37,8 +37,8 @@ void mainboard_fill_dqs_map_data(void *dqs_map_ptr)
 {
 	/* DQS CPU<>DRAM map */
 	const u8 dqs_map[2][8] = {
-		{ 0, 1, 3, 2, 6, 5, 4, 7 },
-		{ 2, 3, 0, 1, 6, 7, 4, 5 } };
+		{ 0, 1, 3, 2, 4, 5, 6, 7 },
+		{ 1, 0, 4, 5, 2, 3, 6, 7 } };
 	memcpy(dqs_map_ptr, dqs_map, sizeof(dqs_map));
 }
 
@@ -94,15 +94,5 @@ uintptr_t mainboard_get_spd_data(void)
 
 int mainboard_has_dual_channel_mem(void)
 {
-	int spd_index;
-
-	spd_index = 0;
-
-	if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN
-		&& spd_index != MIC_SINGLE_CHAN) {
-		printk(BIOS_INFO,
-			"Dual channel SPD detected writing second channel\n");
-		return 1;
-	}
-	return 0;
+	return 1;
 }