[coreboot-gerrit] New patch to review for coreboot: nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17192

-gerrit

commit 614e46de9d930ff393935c9a2d99e56cdfd97b51
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sun Oct 30 18:39:53 2016 +0100

    nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"
    
    Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/northbridge/intel/i945/early_init.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 17fd5a4..57b9896 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -90,9 +90,9 @@ static void i945m_detect_chipset(void)
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC
-	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
-#endif
+
+	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC))
+		printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
 }
 
 static void i945_detect_chipset(void)
@@ -142,9 +142,9 @@ static void i945_detect_chipset(void)
 		printk(BIOS_INFO, "unknown max. RAM clock (%02x).", reg8);	/* Others reserved. */
 	}
 	printk(BIOS_DEBUG, "\n");
-#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM
-	printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
-#endif
+
+	if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM))
+		printk(BIOS_ERR, "coreboot is compiled for the wrong chipset.\n");
 }
 
 static void i945_setup_bars(void)