[coreboot-gerrit] New patch to review for coreboot: google/reef: Set up GPIO_TIER1_SCI_EN properly

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16400

-gerrit

commit 142dc5a3eb64aa944d5afbc0a95bbcbf2bc2e09c
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Thu Sep 1 22:27:15 2016 -0700

    google/reef: Set up GPIO_TIER1_SCI_EN properly
    
    Previously we were setting the gpio_tier1_sci in smihandler before
    going to S3. But this won't work for S0iX as it happens from kernel
    and smi handler is not involved in that flow. We need to set this bit
    i.e. bit 15 in acpi gpe0a register at 0x430h. Kernel before going to
    sleep checks what values are passed through asl as wake events(through _PRW)
    ,keeps those enabled only and clears other bits in gpe0 enable registers.
    So we need to inform kernel to keep gpio_tier_sci also set as these is needed
    for any wake. This patch adds a _PRW method to powerbutton asl code.
    We can use the _PRW method of powerbutton. The reason of choosing powerbutton
    is its the default wake source and does not need any _PRW method defined
    and we cannot define more than one _PRW for any other wake source.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen,powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: Ia9a96f2923bb1720b2fa6eab66832551134c6bea
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/google/reef/acpi/mainboard.asl | 1 +
 src/mainboard/google/reef/gpio.h             | 6 ++++++
 src/mainboard/google/reef/smihandler.c       | 3 ---
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl
index 9665bb2..4111635 100644
--- a/src/mainboard/google/reef/acpi/mainboard.asl
+++ b/src/mainboard/google/reef/acpi/mainboard.asl
@@ -31,6 +31,7 @@ Scope (\_SB)
 	Device (PWRB)
 	{
 		Name (_HID, EisaId ("PNP0C0C"))
+		Name (_PRW, Package() { GPIO_TIER_1_SCI_EN, 0x3 })
 	}
 }
 
diff --git a/src/mainboard/google/reef/gpio.h b/src/mainboard/google/reef/gpio.h
index dbe7062..44bdca4 100644
--- a/src/mainboard/google/reef/gpio.h
+++ b/src/mainboard/google/reef/gpio.h
@@ -21,6 +21,12 @@
 /* Input device interrupt configuration */
 #define TOUCHPAD_INT		GPIO_18_IRQ
 
+/*
+ * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
+ * and/or an SCI or SMI#.
+ */
+#define GPIO_TIER_1_SCI_EN	15
+
 #define BOARD_HP_MIC_CODEC_IRQ	GPIO_116_IRQ
 #define BOARD_HP_MIC_CODEC_I2C_ADDR	0x1a
 
diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index d33222b..d3d6b2b 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -33,9 +33,6 @@ void mainboard_smi_sleep(u8 slp_typ)
 {
 	gpio_configure_pads(sleep_gpio_table, ARRAY_SIZE(sleep_gpio_table));
 
-	if (slp_typ == ACPI_S3)
-		enable_gpe(GPIO_TIER_1_SCI);
-
 	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
 		chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
 					MAINBOARD_EC_S5_WAKE_EVENTS);