[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: Enable lpss s0ix

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16425

-gerrit

commit 1adb40623516147892260e38d214ffb4d0d20977
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date:   Fri Sep 2 16:10:01 2016 -0700

    mainboard/google/reef: Enable lpss s0ix
    
    This setting enables s0ix for lpss
    
    BUG=chrome-os-partner:53876
    
    Change-Id: I2f99035ae41adcb48afd243bbda64262c014c3e8
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
 src/mainboard/google/reef/devicetree.cb | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mainboard/google/reef/devicetree.cb b/src/mainboard/google/reef/devicetree.cb
index 3f763bb..48c9a02 100644
--- a/src/mainboard/google/reef/devicetree.cb
+++ b/src/mainboard/google/reef/devicetree.cb
@@ -43,6 +43,9 @@ chip soc/intel/apollolake
 	register "hdaudio_pwr_gate_enable" = "1"
 	register "hdaudio_bios_config_lockdown" = "1"
 
+	# Enable lpss s0ix
+	register "lpss_s0ix_enable" = "1"
+
 	# GPE configuration
 	# Note that GPE events called out in ASL code rely on this
 	# route, i.e., if this route changes then the affected GPE