[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Configure DW0 and DW1 GPIO registers through ASL
Vaibhav Shankar (vaibhav.shankar@intel.com)
gerrit at coreboot.org
Sat Sep 3 02:21:29 CEST 2016
Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16349
-gerrit
commit 6fd3cd7bd6696b08232a46bd0b1ca1981d06ddd0
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date: Mon Aug 29 14:03:38 2016 -0700
soc/intel/apollolake: Configure DW0 and DW1 GPIO registers through ASL
Implement a function to calculate DW0 register address.
Added GPIO methods to configure DW0 and DW1 registers.
Added GNVS variable and assigned PERST_0 address to GNVS.
BUG=chrome-os-partner:55877
Change-Id: I6eaa1fcecf5970b365e3418541c75b9866959f7e
Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
src/soc/intel/apollolake/acpi.c | 4 ++
src/soc/intel/apollolake/acpi/globalnvs.asl | 1 +
src/soc/intel/apollolake/acpi/gpiolib.asl | 73 +++++++++++++++++++++++++++++
src/soc/intel/apollolake/chip.h | 3 ++
src/soc/intel/apollolake/gpio.c | 15 ++++++
src/soc/intel/apollolake/include/soc/gpio.h | 2 +
src/soc/intel/apollolake/include/soc/nvs.h | 3 +-
7 files changed, 100 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c
index 4f4276a..8829e44 100644
--- a/src/soc/intel/apollolake/acpi.c
+++ b/src/soc/intel/apollolake/acpi.c
@@ -28,6 +28,7 @@
#include <soc/pm.h>
#include <soc/nvs.h>
#include <soc/pci_devs.h>
+#include <soc/gpio.h>
#include "chip.h"
#define CSTATE_RES(address_space, width, offset, address) \
@@ -171,6 +172,9 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs)
/* Set unknown wake source */
gnvs->pm1i = ~0ULL;
+
+ /* Assign address of PERST_0 */
+ gnvs->prt0 = gpio_address(cfg->prt0_gpio);
}
/* Save wake source information for calculating ACPI _SWS values */
diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl
index 404f36c..faff8df 100644
--- a/src/soc/intel/apollolake/acpi/globalnvs.asl
+++ b/src/soc/intel/apollolake/acpi/globalnvs.asl
@@ -38,6 +38,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
GPEI, 64, // 0x11 - 0x18 - GPE Wake Source
NHLA, 64, // 0x19 - 0x20 - NHLT Address
NHLL, 32, // 0x21 - 0x24 - NHLT Length
+ PRAD, 32, // 0x25 - 0x28 - PERST_0 Address
/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
Offset (0x100),
diff --git a/src/soc/intel/apollolake/acpi/gpiolib.asl b/src/soc/intel/apollolake/acpi/gpiolib.asl
new file mode 100644
index 0000000..4dc84ed
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/gpiolib.asl
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+Scope (\_SB)
+{
+
+ /* Get Pad Configuration DW0 register value */
+ Method (GPC0, 0x1, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ Store (Arg0, Local0)
+ OperationRegion (PDW0, SystemMemory,
+ Local0, 4)
+ Field (PDW0, AnyAcc, NoLock, Preserve) {
+ TEMP, 32
+ }
+ Return (TEMP)
+ }
+
+ /* Set Pad Configuration DW0 register value */
+ Method (SPC0, 0x2, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ /* Arg1 - Value for DW0 register */
+ Store (Arg0, Local0)
+ OperationRegion (PDW0, SystemMemory,
+ Local0, 4)
+ Field (PDW0, AnyAcc, NoLock, Preserve) {
+ TEMP,32
+ }
+ Store (Arg1, TEMP)
+ }
+
+ /* Get Pad Configuration DW1 register value */
+ Method (GPC1, 0x1, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ Store ( Add ( Arg0, 0x4), Local0)
+ OperationRegion (PDW1, SystemMemory,
+ Local0, 4)
+ Field (PDW1, AnyAcc, NoLock, Preserve) {
+ TEMP, 32
+ }
+ Return (TEMP)
+ }
+
+
+ /* Set Pad Configuration DW1 register value */
+ Method (SPC1, 0x2, Serialized)
+ {
+ /* Arg0 - GPIO DW0 address */
+ /* Arg1 - Value for DW1 register */
+ Store ( Add ( Arg0, 0x4), Local0)
+ OperationRegion (PDW1, SystemMemory,
+ Local0, 4)
+ Field(PDW1, AnyAcc, NoLock, Preserve) {
+ TEMP,32
+ }
+ Store (Arg1, TEMP)
+ }
+}
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 22217a4..bfd4364 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -109,6 +109,9 @@ struct soc_intel_apollolake_config {
/* SLP S3 minimum assertion width. */
int slp_s3_assertion_width_usecs;
+
+ /* GPIO pin for PERST_0 */
+ uint16_t prt0_gpio;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
diff --git a/src/soc/intel/apollolake/gpio.c b/src/soc/intel/apollolake/gpio.c
index e56f147..0af6fd9 100644
--- a/src/soc/intel/apollolake/gpio.c
+++ b/src/soc/intel/apollolake/gpio.c
@@ -177,6 +177,21 @@ void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads)
gpio_configure_pad(cfg + i);
}
+uint32_t gpio_address(const uint16_t pad)
+{
+ /* Calculate Address of DW0 register for given GPIO
+ * pad - GPIO number
+ * returns - address of GPIO
+ */
+ uint32_t addr;
+ const struct pad_community *comm = gpio_get_community(pad);
+ uint16_t config_offset = PAD_CFG_OFFSET(pad - comm->first_pad);
+
+ addr = (CONFIG_IOSF_BASE_ADDRESS + (comm->port << 16) + config_offset);
+
+ return addr;
+}
+
void gpio_input_pulldown(gpio_t gpio)
{
struct pad_config cfg = PAD_CFG_GPI(gpio, DN_20K, DEEP);
diff --git a/src/soc/intel/apollolake/include/soc/gpio.h b/src/soc/intel/apollolake/include/soc/gpio.h
index 0089444..c7e22b1 100644
--- a/src/soc/intel/apollolake/include/soc/gpio.h
+++ b/src/soc/intel/apollolake/include/soc/gpio.h
@@ -160,6 +160,8 @@ struct pad_config {
void gpio_configure_pad(const struct pad_config *cfg);
void gpio_configure_pads(const struct pad_config *cfg, size_t num_pads);
+/* Calculate GPIO DW0 address */
+uint32_t gpio_address(const uint16_t pad);
/*
* Set the GPIO groups for the GPE blocks. The values from PMC register GPE_CFG
* are passed which is then mapped to proper groups for MISCCFG. This basically
diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h
index bff949e..21894ca 100644
--- a/src/soc/intel/apollolake/include/soc/nvs.h
+++ b/src/soc/intel/apollolake/include/soc/nvs.h
@@ -38,7 +38,8 @@ typedef struct global_nvs_t {
uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */
uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */
uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */
- uint8_t unused[219];
+ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */
+ uint8_t unused[215];
/* ChromeOS specific (0x100 - 0xfff) */
chromeos_acpi_t chromeos;
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