[coreboot-gerrit] Patch set updated for coreboot: src/northbridge: Improve code formatting
HAOUAS Elyes (ehaouas@noos.fr)
gerrit at coreboot.org
Sat Sep 3 14:33:05 CEST 2016
HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16414
-gerrit
commit 4b14c8354aa3c6ef7b00882c5a3c65666910c7da
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date: Fri Sep 2 19:22:00 2016 +0200
src/northbridge: Improve code formatting
Change-Id: Iffa058d9eb1e96a4d1587dc3f8a1740907ffbb32
Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
src/northbridge/amd/agesa/family10/northbridge.c | 10 +-
src/northbridge/amd/agesa/family12/northbridge.c | 316 ++++++++++-----------
src/northbridge/amd/agesa/family15/northbridge.c | 4 +-
src/northbridge/amd/agesa/family15rl/northbridge.c | 4 +-
src/northbridge/amd/agesa/family15tn/northbridge.c | 4 +-
src/northbridge/amd/agesa/family16kb/northbridge.c | 4 +-
src/northbridge/amd/amdfam10/chip.h | 2 +-
src/northbridge/amd/amdht/comlib.c | 48 ++--
src/northbridge/amd/amdht/ht_wrapper.c | 4 +-
src/northbridge/amd/amdk8/amdk8.h | 4 +-
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +-
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 2 +-
src/northbridge/amd/amdmct/wrappers/mcti_d.c | 31 +-
src/northbridge/amd/cimx/rd890/early.c | 2 +-
src/northbridge/amd/pi/00630F01/northbridge.c | 2 +-
src/northbridge/amd/pi/00660F01/northbridge.c | 2 +-
src/northbridge/amd/pi/00730F01/northbridge.c | 2 +-
src/northbridge/intel/e7501/debug.c | 86 +++---
src/northbridge/intel/e7501/northbridge.c | 40 +--
src/northbridge/intel/e7505/debug.c | 86 +++---
src/northbridge/intel/e7505/northbridge.c | 44 +--
src/northbridge/intel/haswell/northbridge.c | 24 +-
src/northbridge/intel/i3100/northbridge.c | 14 +-
src/northbridge/intel/i3100/raminit_ep80579.c | 2 +-
src/northbridge/intel/i5000/raminit.c | 4 +-
src/northbridge/intel/i855/debug.c | 40 +--
src/northbridge/intel/i855/northbridge.c | 66 ++---
src/northbridge/intel/i855/raminit.c | 34 +--
src/northbridge/intel/i945/debug.c | 32 +--
src/northbridge/intel/pineview/gma.c | 30 +-
src/northbridge/intel/x4x/x4x.h | 46 +--
src/northbridge/via/cn700/vga.c | 2 +-
src/northbridge/via/cx700/vga.c | 2 +-
src/northbridge/via/vx800/detection.c | 12 +-
src/northbridge/via/vx800/vga.c | 2 +-
35 files changed, 502 insertions(+), 509 deletions(-)
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c
index 1c8f904..e7bfdd8 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -41,8 +41,8 @@ extern uint32_t agesawrapper_amdinitmid(void);
typedef struct amdfam10_sysconf_t sys_info_conf_t;
typedef struct dram_base_mask {
- u32 base; //[47:27] at [28:8]
- u32 mask; //[47:27] at [28:8] and enable at bit 0
+ u32 base; //[47:27] at [28:8]
+ u32 mask; //[47:27] at [28:8] and enable at bit 0
} dram_base_mask_t;
@@ -218,9 +218,9 @@ static device_t get_node_pci(u32 nodeid, u32 fn)
static unsigned int read_nb_cfg_54(void)
{
- msr_t msr;
- msr = rdmsr(NB_CFG_MSR);
- return (( msr.hi >> (54-32)) & 1);
+ msr_t msr;
+ msr = rdmsr(NB_CFG_MSR);
+ return (( msr.hi >> (54-32)) & 1);
}
static void get_fx_devs(void)
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c
index df6b3e4..1526972 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -269,47 +269,47 @@ struct hw_mem_hole_info {
static struct hw_mem_hole_info get_hw_mem_hole_info(void)
{
- struct hw_mem_hole_info mem_hole;
-
- mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
- mem_hole.node_id = -1;
-
- struct dram_base_mask_t d;
- u32 hole;
- d = get_dram_base_mask(0);
- if (d.mask & 1) {
- hole = pci_read_config32(__f1_dev[0], 0xf0);
- if (hole & 1) { // we find the hole
- mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
- mem_hole.node_id = 0; // record the node No with hole
- }
- }
+ struct hw_mem_hole_info mem_hole;
+
+ mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK;
+ mem_hole.node_id = -1;
+
+ struct dram_base_mask_t d;
+ u32 hole;
+ d = get_dram_base_mask(0);
+ if (d.mask & 1) {
+ hole = pci_read_config32(__f1_dev[0], 0xf0);
+ if (hole & 1) { // we find the hole
+ mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
+ mem_hole.node_id = 0; // record the node No with hole
+ }
+ }
#if 0
/* We need to double check if there is special set on base reg and limit reg
* are not continuous instead of hole, it will find out its hole_startk.
*/
- if (mem_hole.node_id==-1) {
- resource_t limitk_pri = 0;
- struct dram_base_mask_t d;
- resource_t base_k, limit_k;
- d = get_dram_base_mask(0);
- if (d.base & 1) {
- base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
- if (base_k <= 4 *1024 * 1024) {
- if (limitk_pri != base_k) { // we find the hole
- mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
- mem_hole.node_id = 0;
- }
- }
-
- limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
- limitk_pri = limit_k;
- }
- }
+ if (mem_hole.node_id==-1) {
+ resource_t limitk_pri = 0;
+ struct dram_base_mask_t d;
+ resource_t base_k, limit_k;
+ d = get_dram_base_mask(0);
+ if (d.base & 1) {
+ base_k = ((resource_t)(d.base & 0x1fffff00)) <<9;
+ if (base_k <= 4 *1024 * 1024) {
+ if (limitk_pri != base_k) { // we find the hole
+ mem_hole.hole_startk = (unsigned)limitk_pri; // must be below 4G
+ mem_hole.node_id = 0;
+ }
+ }
+
+ limit_k = ((resource_t)((d.mask + 0x00000100) & 0x1fffff00)) << 9;
+ limitk_pri = limit_k;
+ }
+ }
#endif
- return mem_hole;
+ return mem_hole;
}
#endif
@@ -471,44 +471,44 @@ static void setup_uma_memory(void)
static void domain_read_resources(device_t dev)
{
- unsigned reg;
-
- printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
-
- /* Find the already assigned resource pairs */
- get_fx_devs();
- for (reg = 0x80; reg <= 0xc0; reg+= 0x08) {
- u32 base, limit;
- base = f1_read_config32(reg);
- limit = f1_read_config32(reg + 0x04);
- /* Is this register allocated? */
- if ((base & 3) != 0) {
- unsigned nodeid, reg_link;
- device_t reg_dev;
- if (reg<0xc0) { // mmio
- nodeid = (limit & 0xf) + (base&0x30);
- } else { // io
- nodeid = (limit & 0xf) + ((base>>4)&0x30);
- }
- reg_link = (limit >> 4) & 7;
- reg_dev = __f0_dev[nodeid];
- if (reg_dev) {
- /* Reserve the resource */
- struct resource *res;
- res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
- if (res) {
- res->flags = 1;
- }
- }
- }
- }
- /* FIXME: do we need to check extend conf space?
- I don't believe that much preset value */
-
- struct resource *resource;
- /* Initialize the system-wide I/O space constraints. */
+ unsigned reg;
+
+ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
+
+ /* Find the already assigned resource pairs */
+ get_fx_devs();
+ for (reg = 0x80; reg <= 0xc0; reg+= 0x08) {
+ u32 base, limit;
+ base = f1_read_config32(reg);
+ limit = f1_read_config32(reg + 0x04);
+ /* Is this register allocated? */
+ if ((base & 3) != 0) {
+ unsigned nodeid, reg_link;
+ device_t reg_dev;
+ if (reg<0xc0) { // mmio
+ nodeid = (limit & 0xf) + (base&0x30);
+ } else { // io
+ nodeid = (limit & 0xf) + ((base>>4)&0x30);
+ }
+ reg_link = (limit >> 4) & 7;
+ reg_dev = __f0_dev[nodeid];
+ if (reg_dev) {
+ /* Reserve the resource */
+ struct resource *res;
+ res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link));
+ if (res) {
+ res->flags = 1;
+ }
+ }
+ }
+ }
+ /* FIXME: do we need to check extend conf space?
+ I don't believe that much preset value */
+
+ struct resource *resource;
+ /* Initialize the system-wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
- resource->base = 0x1000;
+ resource->base = 0x1000;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
@@ -520,40 +520,40 @@ static void domain_read_resources(device_t dev)
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
- printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
+ printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
}
static void domain_set_resources(device_t dev)
{
- printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
- printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev);
-
- unsigned long mmio_basek;
- u32 pci_tolm;
- u64 ramtop = 0;
- int idx;
- struct bus *link;
+ printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__);
+ printk(BIOS_DEBUG, " amsr - incoming dev = %p\n", dev);
+
+ unsigned long mmio_basek;
+ u32 pci_tolm;
+ u64 ramtop = 0;
+ int idx;
+ struct bus *link;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
- struct hw_mem_hole_info mem_hole;
- u32 reset_memhole = 1;
+ struct hw_mem_hole_info mem_hole;
+ u32 reset_memhole = 1;
#endif
- pci_tolm = 0xffffffffUL;
- for (link = dev->link_list; link; link = link->next) {
- pci_tolm = my_find_pci_tolm(link, pci_tolm);
- }
+ pci_tolm = 0xffffffffUL;
+ for (link = dev->link_list; link; link = link->next) {
+ pci_tolm = my_find_pci_tolm(link, pci_tolm);
+ }
- // FIXME handle interleaved nodes. If you fix this here, please fix
- // amdk8, too.
- mmio_basek = pci_tolm >> 10;
- /* Round mmio_basek to something the processor can support */
- mmio_basek &= ~((1 << 6) -1);
+ // FIXME handle interleaved nodes. If you fix this here, please fix
+ // amdk8, too.
+ mmio_basek = pci_tolm >> 10;
+ /* Round mmio_basek to something the processor can support */
+ mmio_basek &= ~((1 << 6) -1);
- // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
- // MMIO hole. If you fix this here, please fix amdk8, too.
- /* Round the mmio hole to 64M */
- mmio_basek &= ~((64*1024) - 1);
+ // FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M
+ // MMIO hole. If you fix this here, please fix amdk8, too.
+ /* Round the mmio hole to 64M */
+ mmio_basek &= ~((64*1024) - 1);
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
/* if the hw mem hole is already set in raminit stage, here we will compare
@@ -562,77 +562,76 @@ static void domain_set_resources(device_t dev)
* otherwise We reset the hole to the mmio_basek
*/
- mem_hole = get_hw_mem_hole_info();
+ mem_hole = get_hw_mem_hole_info();
- // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
- if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
- mmio_basek = mem_hole.hole_startk;
- reset_memhole = 0;
- }
+ // Use hole_basek as mmio_basek, and we don't need to reset hole anymore
+ if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) {
+ mmio_basek = mem_hole.hole_startk;
+ reset_memhole = 0;
+ }
#endif
- idx = 0x10;
+ idx = 0x10;
- struct dram_base_mask_t d;
- resource_t basek, limitk, sizek; // 4 1T
+ struct dram_base_mask_t d;
+ resource_t basek, limitk, sizek; // 4 1T
- d = get_dram_base_mask(0);
+ d = get_dram_base_mask(0);
- if (d.mask & 1) {
- basek = ((resource_t)(d.base)) << 8;
- limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
-printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
+ if (d.mask & 1) {
+ basek = ((resource_t)(d.base)) << 8;
+ limitk = (resource_t)((d.mask << 8) | 0xFFFFFF);
+ printk(BIOS_DEBUG, "adsr: (before) basek = %llx, limitk = %llx.\n",basek,limitk);
- /* Convert these values to multiples of 1K for ease of math. */
- basek >>= 10;
- limitk >>= 10;
- sizek = limitk - basek + 1;
+ /* Convert these values to multiples of 1K for ease of math. */
+ basek >>= 10;
+ limitk >>= 10;
+ sizek = limitk - basek + 1;
-printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
+ printk(BIOS_DEBUG, "adsr: (after) basek = %llx, limitk = %llx, sizek = %llx.\n",basek,limitk,sizek);
- /* see if we need a hole from 0xa0000 to 0xbffff */
- if ((basek < 640) && (sizek > 768)) {
-printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
- ram_resource(dev, (idx | 0), basek, 640 - basek);
- idx += 0x10;
- basek = 768;
- sizek = limitk - 768;
- }
+ /* see if we need a hole from 0xa0000 to 0xbffff */
+ if ((basek < 640) && (sizek > 768)) {
+ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
+ ram_resource(dev, (idx | 0), basek, 640 - basek);
+ idx += 0x10;
+ basek = 768;
+ sizek = limitk - 768;
+ }
printk(BIOS_DEBUG,
"adsr: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
mmio_basek, basek, limitk);
- /* split the region to accommodate pci memory space */
- if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
- if (basek <= mmio_basek) {
- unsigned pre_sizek;
- pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
- ram_resource(dev, idx, basek, pre_sizek);
- idx += 0x10;
- sizek -= pre_sizek;
- if (!ramtop)
- ramtop = mmio_basek * 1024;
- }
- basek = mmio_basek;
- }
- if ((basek + sizek) <= 4*1024*1024) {
- sizek = 0;
- }
- else {
- basek = 4*1024*1024;
- sizek -= (4*1024*1024 - mmio_basek);
- }
- }
-
- ram_resource(dev, (idx | 0), basek, sizek);
- idx += 0x10;
- printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
- 0, mmio_basek, basek, limitk);
- if (!ramtop)
- ramtop = limitk * 1024;
- }
+ /* split the region to accommodate pci memory space */
+ if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+ if (basek <= mmio_basek) {
+ unsigned pre_sizek;
+ pre_sizek = mmio_basek - basek;
+ if (pre_sizek>0) {
+ ram_resource(dev, idx, basek, pre_sizek);
+ idx += 0x10;
+ sizek -= pre_sizek;
+ if (!ramtop)
+ ramtop = mmio_basek * 1024;
+ }
+ basek = mmio_basek;
+ }
+ if ((basek + sizek) <= 4*1024*1024) {
+ sizek = 0;
+ } else {
+ basek = 4*1024*1024;
+ sizek -= (4*1024*1024 - mmio_basek);
+ }
+ }
+
+ ram_resource(dev, (idx | 0), basek, sizek);
+ idx += 0x10;
+ printk(BIOS_DEBUG, "%d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n",
+ 0, mmio_basek, basek, limitk);
+ if (!ramtop)
+ ramtop = limitk * 1024;
+ }
printk(BIOS_DEBUG, " adsr - mmio_basek = %lx.\n", mmio_basek);
#if CONFIG_GFXUMA
@@ -642,13 +641,12 @@ printk(BIOS_DEBUG, "adsr - 0xa0000 to 0xbffff resource.\n");
set_top_of_ram(ramtop);
#endif
- for (link = dev->link_list; link; link = link->next) {
- if (link->children) {
- assign_resources(link);
- }
- }
-printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
- printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
+ for (link = dev->link_list; link; link = link->next) {
+ if (link->children)
+ assign_resources(link);
+ }
+ printk(BIOS_DEBUG, " adsr - leaving this lovely routine.\n");
+ printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__);
}
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c
index f347b63..0c14bdd 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -1080,9 +1080,9 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
- u8 plat_num_io_apics = 3; /* FIXME */
+ u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c
index ccb256b..d1560b7 100644
--- a/src/northbridge/amd/agesa/family15rl/northbridge.c
+++ b/src/northbridge/amd/agesa/family15rl/northbridge.c
@@ -1070,9 +1070,9 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
- u8 plat_num_io_apics = 3; /* FIXME */
+ u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c
index 63ca2af..7b57cc3 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -1069,9 +1069,9 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
- u8 plat_num_io_apics = 3; /* FIXME */
+ u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c
index c0769e7..28302ef 100644
--- a/src/northbridge/amd/agesa/family16kb/northbridge.c
+++ b/src/northbridge/amd/agesa/family16kb/northbridge.c
@@ -1086,9 +1086,9 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
- u8 plat_num_io_apics = 3; /* FIXME */
+ u8 plat_num_io_apics = 3; /* FIXME */
if ((node_nums * core_max) + plat_num_io_apics >= 0x10) {
lapicid_start = (plat_num_io_apics - 1) / core_max;
diff --git a/src/northbridge/amd/amdfam10/chip.h b/src/northbridge/amd/amdfam10/chip.h
index 60dc00f..daf429d 100644
--- a/src/northbridge/amd/amdfam10/chip.h
+++ b/src/northbridge/amd/amdfam10/chip.h
@@ -19,7 +19,7 @@
#include <stdint.h>
struct northbridge_amd_amdfam10_config {
- uint64_t maximum_memory_capacity;
+ uint64_t maximum_memory_capacity;
};
#endif /* _AMD_FAM10_CHIP_H_ */
diff --git a/src/northbridge/amd/amdht/comlib.c b/src/northbridge/amd/amdht/comlib.c
index e2d158f..64092ff 100644
--- a/src/northbridge/amd/amdht/comlib.c
+++ b/src/northbridge/amd/amdht/comlib.c
@@ -249,38 +249,38 @@ void ErrorStop(u32 value)
;
; For use with SimNow the unrotated error code is also written to port 84h
ErrorStop PROC FAR PASCAL PUBLIC Value:DWORD
- pushad
- mov eax, Value
- mov bx, 0DEADh
- out 84h, eax
+ pushad
+ mov eax, Value
+ mov bx, 0DEADh
+ out 84h, eax
ErrorStopTop:
- out 80h, eax
+ out 80h, eax
- mov cx, 4 ; Rotate the display by one nibble
+ mov cx, 4 ; Rotate the display by one nibble
@@:
- bt bx, 15
- rcl eax, 1
- rcl bx, 1
- loop @B
+ bt bx, 15
+ rcl eax, 1
+ rcl bx, 1
+ loop @B
- push eax ; Delay a few hundred milliseconds
- push ebx
- mov ecx, 10h ; TSC
- db 00Fh, 032h ; RDMSR
- mov ebx, eax
+ push eax ; Delay a few hundred milliseconds
+ push ebx
+ mov ecx, 10h ; TSC
+ db 00Fh, 032h ; RDMSR
+ mov ebx, eax
@@:
- db 00Fh, 032h ; RDMSR
- sub eax, ebx
- cmp eax, 500000000
- jb @B
- pop ebx
- pop eax
+ db 00Fh, 032h ; RDMSR
+ sub eax, ebx
+ cmp eax, 500000000
+ jb @B
+ pop ebx
+ pop eax
- jmp ErrorStopTop
+ jmp ErrorStopTop
- popad
- ret
+ popad
+ ret
ErrorStop ENDP
*/
diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index f31fcd2..0dfc6ab 100644
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -29,9 +29,9 @@
/* Single CPU system? */
#if (CONFIG_MAX_PHYSICAL_CPUS == 1)
/* FIXME
- * This #define is used by other #included .c files
+ * This #define is used by other #included .c files
* When set, multiprocessor support is completely disabled
- */
+ */
#define HT_BUILD_NC_ONLY 1
#endif
diff --git a/src/northbridge/amd/amdk8/amdk8.h b/src/northbridge/amd/amdk8/amdk8.h
index 05117f7..2cde166 100644
--- a/src/northbridge/amd/amdk8/amdk8.h
+++ b/src/northbridge/amd/amdk8/amdk8.h
@@ -6,9 +6,9 @@
#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
- #include "f.h"
+ #include "f.h"
#else
- #include "pre_f.h"
+ #include "pre_f.h"
#endif
#ifdef __PRE_RAM__
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 0c37366..08d8d43 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2398,10 +2398,10 @@ static void precise_ndelay_fam15(struct MCTStatStruc *pMCTstat, uint32_t nanosec
tsc_msr = rdmsr(0x00000010);
start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
- do {
+ do {
tsc_msr = rdmsr(0x00000010);
current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo;
- } while ((current_timestamp - start_timestamp) < cycle_count);
+ } while ((current_timestamp - start_timestamp) < cycle_count);
}
static void precise_memclk_delay_fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t clocks) {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 324e35e..8024179 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -930,7 +930,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
*/
for (lane = 0; lane < 8; lane++) {
if (trained[lane]) {
- pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane];
+ pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1][lane] = current_total_delay[lane];
} else {
printk(BIOS_WARNING, "TrainRcvrEn: WARNING: Lane %d of receiver %d on channel %d failed training!\n", lane, Receiver, Channel);
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 0ba2d33..143468a 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -476,34 +476,31 @@ static void mctHookAfterDramInit(void)
#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
static void vErratum372(struct DCTStatStruc *pDCTstat)
{
- msr_t msr = rdmsr(NB_CFG_MSR);
+ msr_t msr = rdmsr(NB_CFG_MSR);
int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32)));
- // is this the right way to check for NB pstate 1 or DDR3-1333 ?
- if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
- &&(!pDCTstat->GangedMode)) {
- /* DisableCf8ExtCfg */
- msr.hi &= ~(3 << (51 - 32));
- wrmsr(NB_CFG_MSR, msr);
- }
+ // is this the right way to check for NB pstate 1 or DDR3-1333 ?
+ if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
+ &&(!pDCTstat->GangedMode)) {
+ /* DisableCf8ExtCfg */
+ msr.hi &= ~(3 << (51 - 32));
+ wrmsr(NB_CFG_MSR, msr);
+ }
}
static void vErratum414(struct DCTStatStruc *pDCTstat)
{
- int dct=0;
- for (; dct < 2 ; dct++)
- {
- int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
+ int dct=0;
+ for (; dct < 2 ; dct++) {
+ int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
int powerDown = dRAMConfigHi & (1 << PowerDownEn );
int ddr3 = dRAMConfigHi & (1 << Ddr3Mode );
- int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
+ int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel);
- if (powerDown && ddr3 && pchgPDModeSel )
- {
- Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
+ if (powerDown && ddr3 && pchgPDModeSel )
+ Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
}
- }
}
#endif
diff --git a/src/northbridge/amd/cimx/rd890/early.c b/src/northbridge/amd/cimx/rd890/early.c
index 5852aa3..4904e52 100644
--- a/src/northbridge/amd/cimx/rd890/early.c
+++ b/src/northbridge/amd/cimx/rd890/early.c
@@ -34,7 +34,7 @@ void sr56x0_rd890_disable_pcie_bridge(void)
AMD_NB_CONFIG_BLOCK *cfg_ptr = &cfg_block;
AMD_NB_CONFIG *nb_cfg = &(cfg_block.Northbridges[0]);
- nb_cfg->ConfigPtr = &cfg_ptr;
+ nb_cfg->ConfigPtr = &cfg_ptr;
nb_dev = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
val = (1 << 2) | (1 << 3); /*GPP1*/
val |= (1 << 4) | (1 << 5) | (1 << 6) | (1 << 7) | (1 << 16) | (1 << 17); /*GPP3a*/
diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c
index c55cefb..0f9e5f5 100644
--- a/src/northbridge/amd/pi/00630F01/northbridge.c
+++ b/src/northbridge/amd/pi/00630F01/northbridge.c
@@ -1077,7 +1077,7 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c
index 1caecf9..efee0a4 100644
--- a/src/northbridge/amd/pi/00660F01/northbridge.c
+++ b/src/northbridge/amd/pi/00660F01/northbridge.c
@@ -1077,7 +1077,7 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c
index 6f7f993..6d5418a 100644
--- a/src/northbridge/amd/pi/00730F01/northbridge.c
+++ b/src/northbridge/amd/pi/00730F01/northbridge.c
@@ -1108,7 +1108,7 @@ static void cpu_bus_scan(device_t dev)
*
* This is needed because many IO-APIC devices only have 4 bits
* for their APIC id and therefore must reside at 0..15
- */
+ */
if ((node_nums * core_max) + ioapic_count >= 0x10) {
lapicid_start = (ioapic_count - 1) / core_max;
lapicid_start = (lapicid_start + 1) * core_max;
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index af9a8bf..cf14fd1 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -35,7 +35,7 @@ static void dump_pci_device(unsigned dev)
for (i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0)
- printk(BIOS_DEBUG, "\n%02x:",i);
+ printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
@@ -61,19 +61,19 @@ static inline void dump_pci_devices(void)
static inline void dump_pci_devices_on_bus(unsigned busn)
{
- device_t dev;
- for (dev = PCI_DEV(busn, 0, 0);
- dev <= PCI_DEV(busn, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
+ device_t dev;
+ for (dev = PCI_DEV(busn, 0, 0);
+ dev <= PCI_DEV(busn, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
}
static inline void dump_spd_registers(const struct mem_controller *ctrl)
@@ -103,18 +103,18 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel1[i];
if (device) {
int j;
- printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
+ printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
for (j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
@@ -123,24 +123,24 @@ static inline void dump_spd_registers(const struct mem_controller *ctrl)
static inline void dump_smbus_registers(void)
{
unsigned device;
- printk(BIOS_DEBUG, "\n");
- for (device = 1; device < 0x80; device++) {
- int j;
+ printk(BIOS_DEBUG, "\n");
+ for (device = 1; device < 0x80; device++) {
+ int j;
if ( smbus_read_byte(device, 0) < 0 ) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- status = smbus_read_byte(device, j);
- if (status < 0) {
+ for (j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
break;
- }
- if ((j & 0xf) == 0)
+ }
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
- byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
+ byte = status & 0xff;
+ printk(BIOS_DEBUG, "%02x ", byte);
+ }
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -149,28 +149,28 @@ static inline void dump_io_resources(unsigned port)
int i;
printk(BIOS_DEBUG, "%04x:\n", port);
- for (i=0;i<256;i++) {
- uint8_t val;
- if ((i & 0x0f) == 0)
+ for (i=0;i<256;i++) {
+ uint8_t val;
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
- val = inb(port);
+ val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
- if ((i & 0x0f) == 0x0f) {
- printk(BIOS_DEBUG, "\n");
- }
+ if ((i & 0x0f) == 0x0f) {
+ printk(BIOS_DEBUG, "\n");
+ }
port++;
- }
+ }
}
static inline void dump_mem(unsigned start, unsigned end)
{
- unsigned i;
+ unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
+ for (i=start;i<end;i++) {
if ((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
}
#endif
diff --git a/src/northbridge/intel/e7501/northbridge.c b/src/northbridge/intel/e7501/northbridge.c
index 5296bdb..d4f77ae 100644
--- a/src/northbridge/intel/e7501/northbridge.c
+++ b/src/northbridge/intel/e7501/northbridge.c
@@ -23,9 +23,9 @@ unsigned long acpi_fill_mcfg(unsigned long current)
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@@ -102,36 +102,36 @@ static void pci_domain_set_resources(device_t dev)
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_e7501_ops = {
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 33f1ed1..e20d676 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -45,7 +45,7 @@ void dump_pci_device(unsigned dev)
for (i = 0; i < 256; i++) {
unsigned char val;
if ((i & 0x0f) == 0)
- printk(BIOS_DEBUG, "\n%02x:",i);
+ printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
@@ -71,19 +71,19 @@ void dump_pci_devices(void)
void dump_pci_devices_on_bus(unsigned busn)
{
- device_t dev;
- for (dev = PCI_DEV(busn, 0, 0);
- dev <= PCI_DEV(busn, 0x1f, 0x7);
- dev += PCI_DEV(0,0,1)) {
- uint32_t id;
- id = pci_read_config32(dev, PCI_VENDOR_ID);
- if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0xffff) ||
- (((id >> 16) & 0xffff) == 0x0000)) {
- continue;
- }
- dump_pci_device(dev);
- }
+ device_t dev;
+ for (dev = PCI_DEV(busn, 0, 0);
+ dev <= PCI_DEV(busn, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
}
void dump_spd_registers(const struct mem_controller *ctrl)
@@ -113,18 +113,18 @@ void dump_spd_registers(const struct mem_controller *ctrl)
device = ctrl->channel1[i];
if (device) {
int j;
- printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
+ printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
for (j = 0; j < 128; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
+ printk(BIOS_DEBUG, "%02x ", byte);
}
printk(BIOS_DEBUG, "\n");
}
@@ -133,24 +133,24 @@ void dump_spd_registers(const struct mem_controller *ctrl)
void dump_smbus_registers(void)
{
unsigned device;
- printk(BIOS_DEBUG, "\n");
- for (device = 1; device < 0x80; device++) {
- int j;
+ printk(BIOS_DEBUG, "\n");
+ for (device = 1; device < 0x80; device++) {
+ int j;
if ( spd_read_byte(device, 0) < 0 ) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- status = spd_read_byte(device, j);
- if (status < 0) {
+ for (j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ status = spd_read_byte(device, j);
+ if (status < 0) {
break;
- }
- if ((j & 0xf) == 0)
+ }
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
- byte = status & 0xff;
- printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
+ byte = status & 0xff;
+ printk(BIOS_DEBUG, "%02x ", byte);
+ }
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -159,27 +159,27 @@ void dump_io_resources(unsigned port)
int i;
printk(BIOS_DEBUG, "%04x:\n", port);
- for (i=0;i<256;i++) {
- uint8_t val;
- if ((i & 0x0f) == 0)
+ for (i=0;i<256;i++) {
+ uint8_t val;
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
- val = inb(port);
+ val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
- if ((i & 0x0f) == 0x0f) {
- printk(BIOS_DEBUG, "\n");
- }
+ if ((i & 0x0f) == 0x0f) {
+ printk(BIOS_DEBUG, "\n");
+ }
port++;
- }
+ }
}
void dump_mem(unsigned start, unsigned end)
{
- unsigned i;
+ unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
+ for (i=start;i<end;i++) {
if ((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/intel/e7505/northbridge.c b/src/northbridge/intel/e7505/northbridge.c
index 4a3e993..71b19f6 100644
--- a/src/northbridge/intel/e7505/northbridge.c
+++ b/src/northbridge/intel/e7505/northbridge.c
@@ -12,16 +12,16 @@
unsigned long acpi_fill_mcfg(unsigned long current)
{
- /* Just a dummy */
- return current;
+ /* Just a dummy */
+ return current;
}
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
@@ -108,37 +108,37 @@ static struct pci_operations intel_pci_ops = {
};
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
.ops_pci = &intel_pci_ops,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_e7505_ops = {
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c
index 4af6e11..d4b6e90 100644
--- a/src/northbridge/intel/haswell/northbridge.c
+++ b/src/northbridge/intel/haswell/northbridge.c
@@ -101,8 +101,7 @@ static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len)
/* There are special BARs that actually are programmed in the MCHBAR. These
* Intel special features, but they do consume resources that need to be
* accounted for. */
-static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base,
- u32 *len)
+static int get_bar_in_mchbar(device_t dev, unsigned int index, u32 *base, u32 *len)
{
u32 bar;
@@ -122,7 +121,7 @@ struct fixed_mmio_descriptor {
unsigned int index;
u32 size;
int (*get_resource)(device_t dev, unsigned int index,
- u32 *base, u32 *size);
+ u32 *base, u32 *size);
const char *description;
};
@@ -154,13 +153,13 @@ static void mc_add_fixed_mmio_resources(device_t dev)
size = mc_fixed_resources[i].size;
index = mc_fixed_resources[i].index;
if (!mc_fixed_resources[i].get_resource(dev, index,
- &base, &size))
+ &base, &size))
continue;
resource = new_resource(dev, mc_fixed_resources[i].index);
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
resource->base = base;
resource->size = size;
printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n",
@@ -198,8 +197,7 @@ struct map_entry {
const char *description;
};
-static void read_map_entry(device_t dev, struct map_entry *entry,
- uint64_t *result)
+static void read_map_entry(device_t dev, struct map_entry *entry, uint64_t *result)
{
uint64_t value;
uint64_t mask;
@@ -345,16 +343,16 @@ static void mc_add_dram_resources(device_t dev)
resource->base = mc_values[TSEG_REG];
resource->size = mc_values[BGSM_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE;
/* BGSM -> TOLUD */
resource = new_resource(dev, index++);
resource->base = mc_values[BGSM_REG];
resource->size = mc_values[TOLUD_REG] - resource->base;
resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
- IORESOURCE_STORED | IORESOURCE_RESERVE |
- IORESOURCE_ASSIGNED;
+ IORESOURCE_STORED | IORESOURCE_RESERVE |
+ IORESOURCE_ASSIGNED;
/* 4GiB -> TOUUD */
base_k = 4096 * 1024; /* 4GiB */
@@ -370,7 +368,7 @@ static void mc_add_dram_resources(device_t dev)
*/
mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10);
reserved_ram_resource(dev, index++, (0xc0000 >> 10),
- (0x100000 - 0xc0000) >> 10);
+ (0x100000 - 0xc0000) >> 10);
#if CONFIG_CHROMEOS_RAMOOPS
reserved_ram_resource(dev, index++,
CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c
index c8e3221..a48d8fe 100644
--- a/src/northbridge/intel/i3100/northbridge.c
+++ b/src/northbridge/intel/i3100/northbridge.c
@@ -40,7 +40,7 @@ static void pci_domain_set_resources(device_t dev)
device_t mc_dev;
u32 pci_tolm;
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
#if 1
printk(BIOS_DEBUG, "PCI mem marker = %x\n", pci_tolm);
@@ -211,15 +211,15 @@ static const struct pci_driver mc_driver __pci_driver = {
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 497339c..001ec0d 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -618,7 +618,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
- }
+ }
udelay(16);
/* No command */
diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c
index ef49380..ed3f0b4 100644
--- a/src/northbridge/intel/i5000/raminit.c
+++ b/src/northbridge/intel/i5000/raminit.c
@@ -599,7 +599,7 @@ static int i5000_ddr_init(struct i5000_fbdimm *d)
val = (d->setup->t_al << 19) |
((odt & 1) << 18) |
- ((odt & 2) << 21) | 1;
+ ((odt & 2) << 21) | 1;
printk(BIOS_DEBUG, "EMRS(1): 0x%08x\n", val);
@@ -1268,7 +1268,7 @@ static void i5000_setup_interleave(struct i5000_fbd_setup *setup)
mir0 = (size0 << 1) | 3;
mir1 = (size0 << 1);
mir2 = (size0 << 1);
- } else if (!size0) {
+ } else if (!size0) {
mir0 = size1 | 1;
mir1 = size1;
mir2 = size1;
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 05e934d..2a9e407 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -104,26 +104,26 @@ static inline void dump_spd_registers(void)
static inline void dump_smbus_registers(void)
{
- int i;
- printk(BIOS_DEBUG, "\n");
- for (i = 1; i < 0x80; i++) {
- unsigned device;
- device = i;
- int j;
- printk(BIOS_DEBUG, "smbus: %02x", device);
- for (j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0)
- printk(BIOS_DEBUG, "\n%02x: ", j);
- status = smbus_read_byte(device, j);
- if (status < 0) {
- printk(BIOS_DEBUG, "bad device\n");
- break;
- }
- byte = status & 0xff;
+ int i;
+ printk(BIOS_DEBUG, "\n");
+ for (i = 1; i < 0x80; i++) {
+ unsigned device;
+ device = i;
+ int j;
+ printk(BIOS_DEBUG, "smbus: %02x", device);
+ for (j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ printk(BIOS_DEBUG, "bad device\n");
+ break;
+ }
+ byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
- }
- printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i855/northbridge.c b/src/northbridge/intel/i855/northbridge.c
index e9b1cac..bc497a8 100644
--- a/src/northbridge/intel/i855/northbridge.c
+++ b/src/northbridge/intel/i855/northbridge.c
@@ -30,33 +30,33 @@
static void northbridge_init(device_t dev)
{
- printk(BIOS_SPEW, "Northbridge init\n");
+ printk(BIOS_SPEW, "Northbridge init\n");
}
static struct device_operations northbridge_operations = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = northbridge_init,
- .enable = 0,
- .ops_pci = 0,
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = northbridge_init,
+ .enable = 0,
+ .ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &northbridge_operations,
- .vendor = PCI_VENDOR_ID_INTEL,
- .device = 0x3580,
+ .ops = &northbridge_operations,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = 0x3580,
};
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
- uint32_t pci_tolm;
+ uint32_t pci_tolm;
- printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
+ printk(BIOS_DEBUG, "Entered with dev vid = %x\n", dev->vendor);
printk(BIOS_DEBUG, "Entered with dev did = %x\n", dev->device);
- pci_tolm = find_pci_tolm(dev->link_list);
+ pci_tolm = find_pci_tolm(dev->link_list);
mc_dev = dev->link_list->children->sibling;
printk(BIOS_DEBUG, "MC dev vendor = %x\n", mc_dev->vendor);
printk(BIOS_DEBUG, "MC dev device = %x\n", mc_dev->device);
@@ -107,39 +107,39 @@ static void pci_domain_set_resources(device_t dev)
}
static struct device_operations pci_domain_ops = {
- .read_resources = pci_domain_read_resources,
- .set_resources = pci_domain_set_resources,
- .enable_resources = NULL,
- .init = NULL,
- .scan_bus = pci_domain_scan_bus,
- .ops_pci_bus = pci_bus_default_ops,
+ .read_resources = pci_domain_read_resources,
+ .set_resources = pci_domain_set_resources,
+ .enable_resources = NULL,
+ .init = NULL,
+ .scan_bus = pci_domain_scan_bus,
+ .ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
- initialize_cpus(dev->link_list);
+ initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
- .read_resources = DEVICE_NOOP,
- .set_resources = DEVICE_NOOP,
- .enable_resources = DEVICE_NOOP,
- .init = cpu_bus_init,
- .scan_bus = 0,
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .init = cpu_bus_init,
+ .scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
- /* Set the operations if it is a special bus type */
- if (dev->path.type == DEVICE_PATH_DOMAIN) {
- dev->ops = &pci_domain_ops;
- }
- else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
- dev->ops = &cpu_bus_ops;
- }
+ /* Set the operations if it is a special bus type */
+ if (dev->path.type == DEVICE_PATH_DOMAIN) {
+ dev->ops = &pci_domain_ops;
+ }
+ else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
+ dev->ops = &cpu_bus_ops;
+ }
}
struct chip_operations northbridge_intel_i855_ops = {
- CHIP_NAME("Intel 855 Northbridge")
+ CHIP_NAME("Intel 855 Northbridge")
.enable_dev = enable_dev,
};
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index fe6059d..43400ab 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -369,32 +369,32 @@ static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits)
PRINTK_DEBUG(" Sending RAM command 0x%08x\n", reg32);
pci_write_config32(NORTHBRIDGE_MMC, DRC, reg32);
- // RAM_COMMAND_NORMAL is an exception.
- // It affects only the memory controller and does not need to be "sent" to the DIMMs.
+ // RAM_COMMAND_NORMAL is an exception.
+ // It affects only the memory controller and does not need to be "sent" to the DIMMs.
- if (command != RAM_COMMAND_NORMAL) {
+ if (command != RAM_COMMAND_NORMAL) {
- // Send the command to all DIMMs by accessing a memory location within each
- // NOTE: for mode select commands, some of the location address bits
- // are part of the command
+ // Send the command to all DIMMs by accessing a memory location within each
+ // NOTE: for mode select commands, some of the location address bits
+ // are part of the command
- // Map JEDEC mode bits to i855
- if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
+ // Map JEDEC mode bits to i855
+ if (command == RAM_COMMAND_MRS || command == RAM_COMMAND_EMRS) {
/* Host address lines [13:3] map to DIMM address lines [11, 9:0] */
i855_mode_bits = ((jedec_mode_bits & 0x800) << (13 - 11)) | ((jedec_mode_bits & 0x3ff) << (12 - 9));
- }
+ }
- for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
- uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
- if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
+ for (i = 0; i < (DIMM_SOCKETS * 2); ++i) {
+ uint8_t dimm_end_32M_multiple = pci_read_config8(NORTHBRIDGE_MMC, DRB + i);
+ if (dimm_end_32M_multiple > dimm_start_32M_multiple) {
- uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
+ uint32_t dimm_start_address = dimm_start_32M_multiple << 25;
PRINTK_DEBUG(" Sending RAM command to 0x%08x\n", dimm_start_address + i855_mode_bits);
- read32((void *)(dimm_start_address + i855_mode_bits));
+ read32((void *)(dimm_start_address + i855_mode_bits));
- // Set the start of the next DIMM
- dimm_start_32M_multiple = dimm_end_32M_multiple;
- }
+ // Set the start of the next DIMM
+ dimm_start_32M_multiple = dimm_end_32M_multiple;
+ }
}
}
}
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index 5b6c87a..f75c368 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -78,21 +78,21 @@ void dump_pci_devices(void)
void dump_spd_registers(void)
{
- unsigned device;
- device = DIMM0;
- while (device <= DIMM3) {
- int status = 0;
- int i;
- printk(BIOS_DEBUG, "\ndimm %02x", device);
+ unsigned device;
+ device = DIMM0;
+ while (device <= DIMM3) {
+ int status = 0;
+ int i;
+ printk(BIOS_DEBUG, "\ndimm %02x", device);
- for (i = 0; (i < 256) ; i++) {
- if ((i % 16) == 0) {
+ for (i = 0; (i < 256) ; i++) {
+ if ((i % 16) == 0) {
printk(BIOS_DEBUG, "\n%02x: ", i);
- }
+ }
status = smbus_read_byte(device, i);
- if (status < 0) {
- printk(BIOS_DEBUG, "bad device: %02x\n", -status);
- break;
+ if (status < 0) {
+ printk(BIOS_DEBUG, "bad device: %02x\n", -status);
+ break;
}
printk(BIOS_DEBUG, "%02x ", status);
}
@@ -103,13 +103,13 @@ void dump_spd_registers(void)
void dump_mem(unsigned start, unsigned end)
{
- unsigned i;
+ unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
+ for (i=start;i<end;i++) {
if ((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
- }
- printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index 989f5ef..335e38a 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -46,31 +46,31 @@
#define PGETBL_ENABLED 0x1
#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
- ADPA_CRT_HOTPLUG_WARMUP_10MS | \
- ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
- ADPA_CRT_HOTPLUG_SAMPLE_4S | \
- ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
- ADPA_CRT_HOTPLUG_VOLREF_325MV | \
- ADPA_CRT_HOTPLUG_ENABLE)
+ ADPA_CRT_HOTPLUG_WARMUP_10MS | \
+ ADPA_CRT_HOTPLUG_MONITOR_COLOR| \
+ ADPA_CRT_HOTPLUG_SAMPLE_4S | \
+ ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
+ ADPA_CRT_HOTPLUG_VOLREF_325MV | \
+ ADPA_CRT_HOTPLUG_ENABLE)
static struct resource *gtt_res = NULL;
static struct resource *mmio_res = NULL;
static int gtt_setup(u8 *mmiobase)
{
- u32 gttbase;
- device_t dev = dev_find_slot(0, PCI_DEVFN(0,0));
+ u32 gttbase;
+ device_t dev = dev_find_slot(0, PCI_DEVFN(0,0));
- gttbase = pci_read_config32(dev, BGSM);
- printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
+ gttbase = pci_read_config32(dev, BGSM);
+ printk(BIOS_DEBUG, "gttbase = %08x\n", gttbase);
- write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
- udelay(50);
- write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+ write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
+ udelay(50);
+ write32(mmiobase + PGETBL_CTL, gttbase | PGETBL_512KB);
- write32(mmiobase + GFX_FLSH_CNTL, 0);
+ write32(mmiobase + GFX_FLSH_CNTL, 0);
- return 0;
+ return 0;
}
static void intel_gma_init(const struct northbridge_intel_pineview_config *info,
diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h
index e02ee02..4c61e1c 100644
--- a/src/northbridge/intel/x4x/x4x.h
+++ b/src/northbridge/intel/x4x/x4x.h
@@ -289,29 +289,29 @@ struct sysinfo {
};
enum ddr2_signals {
- CLKSET0 = 0,
- CTRL0,
- CLKSET1,
- CMD,
- CTRL1,
- CTRL2,
- CTRL3,
- DQS1,
- DQS2,
- DQS3,
- DQS4,
- DQS5,
- DQS6,
- DQS7,
- DQS8,
- DQ1,
- DQ2,
- DQ3,
- DQ4,
- DQ5,
- DQ6,
- DQ7,
- DQ8
+ CLKSET0 = 0,
+ CTRL0,
+ CLKSET1,
+ CMD,
+ CTRL1,
+ CTRL2,
+ CTRL3,
+ DQS1,
+ DQS2,
+ DQS3,
+ DQS4,
+ DQS5,
+ DQS6,
+ DQS7,
+ DQS8,
+ DQ1,
+ DQ2,
+ DQ3,
+ DQ4,
+ DQ5,
+ DQ6,
+ DQ7,
+ DQ8
};
#ifndef __BOOTBLOCK__
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index 2e453dc..10b7f65 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -64,7 +64,7 @@ static int via_cn700_int15_handler(void)
case 0x5f0f:
X86_EAX=0x860f;
break;
- default:
+ default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
X86_EAX & 0xffff);
break;
diff --git a/src/northbridge/via/cx700/vga.c b/src/northbridge/via/cx700/vga.c
index 7f9d286..16f0ea0 100644
--- a/src/northbridge/via/cx700/vga.c
+++ b/src/northbridge/via/cx700/vga.c
@@ -116,7 +116,7 @@ static int via_cx700_int15_handler(void)
res=1;
break;
- default:
+ default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
X86_EAX & 0xffff);
break;
diff --git a/src/northbridge/via/vx800/detection.c b/src/northbridge/via/vx800/detection.c
index c2397c8..ce643a0 100644
--- a/src/northbridge/via/vx800/detection.c
+++ b/src/northbridge/via/vx800/detection.c
@@ -146,16 +146,16 @@ CB_STATUS GetInfoFromSPD(DRAM_SYS_ATTR *DramAttr)
LoadNum = (u8) (ModuleDataWidth / ChipWidth);
/* Set the RANK map. */
- /* Get bit0,1, the most number of supported RANK is 2. */
+ /* Get bit0,1, the most number of supported RANK is 2. */
RankNum = (u8) (pSPDDataBuf[SPD_SDRAM_DIMM_RANKS] & 0x3);
if (RAMTYPE_SDRAMDDR2 == DramAttr->DramType)
- /*
- * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK
- * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK
- */
+ /*
+ * For DDR bit[0,1]: 01->1 RANK, 10->2 RANK
+ * For DDR2 bit[0,1]: 00->1 RANK, 01->2 RANK
+ */
RankNum++;
- /* Every DIMM have 1 or 2 ranks. */
+ /* Every DIMM have 1 or 2 ranks. */
if (RankNum != 2 && RankNum != 1) {
Status = CB_DEVICE_ERROR;
PRINT_DEBUG_MEM("Memory Device ERROR: Number "
diff --git a/src/northbridge/via/vx800/vga.c b/src/northbridge/via/vx800/vga.c
index f02236d..61d4563 100644
--- a/src/northbridge/via/vx800/vga.c
+++ b/src/northbridge/via/vx800/vga.c
@@ -114,7 +114,7 @@ static int via_vx800_int15_handler(void)
X86_EAX = 0x005f;
res = 1;
break;
- default:
+ default:
printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n",
X86_EAX & 0xffff);
X86_EAX = 0;
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