[coreboot-gerrit] New patch to review for coreboot: nb/intel/x4x: Fix DMI init

[Damien Zammit (damien@zamaudio.com)]

Damien Zammit (damien at zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16491

-gerrit

commit 6d9b310a447ebd9104689d6e8acfa56b6647e189
Author: Damien Zammit <damien at zamaudio.com>
Date:   Sun Sep 4 23:49:10 2016 +1000

    nb/intel/x4x: Fix DMI init
    
    No more hang on DMI init when loop for DMI is re-enabled.
    
    Need to test this on GA-G41M-ES2L to see if PCIe add-on cards
    are now working or not.
    
    Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd
    Signed-off-by: Damien Zammit <damien at zamaudio.com>
---
 src/northbridge/intel/x4x/pcie.c | 148 ++++++++++++++++++++++++++++++++++++---
 1 file changed, 137 insertions(+), 11 deletions(-)

diff --git a/src/northbridge/intel/x4x/pcie.c b/src/northbridge/intel/x4x/pcie.c
index d432fea..0dd5313 100644
--- a/src/northbridge/intel/x4x/pcie.c
+++ b/src/northbridge/intel/x4x/pcie.c
@@ -26,42 +26,168 @@
 #include "x4x.h"
 
 #define DEFAULT_RCBA	0xfed1c000
+#define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
+#define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
+#define RCBA32(x) *((volatile u32 *)(DEFAULT_RCBA + x))
 
 static void init_egress(void)
 {
+	const u32 v2c_800 = 0x00014514;
+	const u32 v2c_1066 = 0x0001a6db;
+	const u32 v2c_1333 = 0x00022861;
+	u32 reg32;
+
 	/* VC0: TC0 only */
 	EPBAR8(0x14) = 1;
 	EPBAR8(0x4) = 1;
 
+	switch (MCHBAR32(0xc00) & 0x7) {
+	case 0x0:
+		// FSB 1066
+		EPBAR32(0x2c) = v2c_1066;
+		break;
+	case 0x2:
+		// FSB 800
+		EPBAR32(0x2c) = v2c_800;
+		break;
+	default:
+	case 0x4:
+		// FSB 1333
+		EPBAR32(0x2c) = v2c_1333;
+		break;
+	}
+	EPBAR32(0x28) = 0x0a0a0a0a;
+	EPBAR8(0xc) = (EPBAR8(0xc) & ~0xe) | 2;
+	EPBAR32(0x1c) = (EPBAR32(0x1c) & ~0x7f0000) | 0x0a0000;
+	MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7;
+
 	/* VC1: ID1, TC7 */
-	EPBAR32(0x20) = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
-	EPBAR8(0x20) = 1 << 7;
+	reg32 = (EPBAR32(0x20) & ~(7 << 24)) | (1 << 24);
+	reg32 = (reg32 & ~0xfe) | (1 << 7);
+	EPBAR32(0x20) = reg32;
+
+	/* Init VC1 port arbitration table */
+	EPBAR32(0x100) = 0x001000001;
+	EPBAR32(0x104) = 0x000040000;
+	EPBAR32(0x108) = 0x000001000;
+	EPBAR32(0x10c) = 0x000000040;
+	EPBAR32(0x110) = 0x001000001;
+	EPBAR32(0x114) = 0x000040000;
+	EPBAR32(0x118) = 0x000001000;
+	EPBAR32(0x11c) = 0x000000040;
+
+	/* Load table */
+	reg32 = EPBAR32(0x20) | (1 << 16);
+	EPBAR32(0x20) = reg32;
+	asm("nop");
+	EPBAR32(0x20) = reg32;
+
+	/* Wait for table load */
+	while ((EPBAR8(0x26) & (1 << 0)) != 0) ;
 
 	/* VC1: enable */
 	EPBAR32(0x20) |= 1 << 31;
 
-	while ((EPBAR8(0x26) & 2) != 0) ;
+	/* Wait for VC1 */
+	while ((EPBAR8(0x26) & (1 << 1)) != 0) ;
 
-	printk(BIOS_DEBUG, "Done EP loop\n");
+	printk(BIOS_DEBUG, "Done Egress Port\n");
 }
 
 static void init_dmi(void)
 {
+	u32 reg32;
+	u16 reg16;
+
+	/* Assume IGD present */
+
+	/* Clear error status */
+	DMIBAR32(0x1c4) = 0xffffffff;
+	DMIBAR32(0x1d0) = 0xffffffff;
+
 	/* VC0: TC0 only */
 	DMIBAR8(DMIVC0RCTL) = 1;
 	DMIBAR8(0x4) = 1;
 
 	/* VC1: ID1, TC7 */
-	DMIBAR32(DMIVC1RCTL) = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
-	DMIBAR8(DMIVC1RCTL) = 1 << 7;
+	reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
+	reg32 = (reg32 & ~0xff) | 1 << 7;
 
 	/* VC1: enable */
-	DMIBAR32(DMIVC1RCTL) |= 1 << 31;
+	reg32 |= 1 << 31;
+	reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
+
+	DMIBAR32(DMIVC1RCTL) = reg32;
+
+	/* Southbridge RCBA setup */
+	RCBA8(0x3022) &= ~1;
+
+	reg32 = (0x5 << 28) | (1 << 6); // PCIe x4
+	RCBA32(0x2020) = (RCBA32(0x2020) & ~((0xf << 28) | (0x7 << 6))) | reg32;
+
+	/* Assign VC1 id 1 */
+	RCBA32(0x20) = (RCBA32(0x20) & ~(0x7 << 24)) | (1 << 24);
+
+	/* Map TC7 to VC1 */
+	RCBA8(0x20) &= 1;
+	RCBA8(0x20) |= 1 << 7;
 
-	// Hangs
-	//while ((DMIBAR8(0x26) & 2) != 0) ;
-	//printk(BIOS_DEBUG, "Done DMI loop\n");
+	/* Map TC0 to VC0 */
+	RCBA8(0x14) &= 1;
 
+	/* Init DMI VC1 port arbitration table */
+	RCBA32(0x20) &= 0xfff1ffff;
+	RCBA32(0x20) |= 1 << 19;
+
+	RCBA32(0x30) = 0x0000000f;
+	RCBA32(0x34) = 0x000f0000;
+	RCBA32(0x38) = 0;
+	RCBA32(0x3c) = 0x000000f0;
+	RCBA32(0x40) = 0x0f000000;
+	RCBA32(0x44) = 0;
+	RCBA32(0x48) = 0x0000f000;
+	RCBA32(0x4c) = 0;
+	RCBA32(0x50) = 0x0000000f;
+	RCBA32(0x54) = 0x000f0000;
+	RCBA32(0x58) = 0;
+	RCBA32(0x5c) = 0x000000f0;
+	RCBA32(0x60) = 0x0f000000;
+	RCBA32(0x64) = 0;
+	RCBA32(0x68) = 0x0000f000;
+	RCBA32(0x6c) = 0;
+
+	RCBA32(0x20) |= 1 << 16;
+
+	/* Enable VC1 */
+	RCBA32(0x20) |= 1 << 31;
+
+	/* Wait for VC1 */
+	while ((RCBA8(0x26) & (1 << 1)) != 0);
+
+	/* Wait for table load */
+	while ((RCBA8(0x26) & (1 << 0)) != 0);
+
+	/* ASPM on DMI link */
+	RCBA16(0x1a8) &= ~0x3;
+	reg16 = RCBA16(0x1a8);
+	RCBA32(0x2010) = (RCBA32(0x2010) & ~(0x3 << 10)) | (1 << 10);
+	reg32 = RCBA32(0x2010);
+
+	/* Set up VC1 max time */
+	RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
+
+	while ((DMIBAR32(0x26) & (1 << 1)) != 0);
+	printk(BIOS_DEBUG, "Done DMI setup\n");
+
+	/* ASPM on DMI */
+	DMIBAR32(0x200) &= ~(0x3 << 26);
+	DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
+	DMIBAR32(0x88) &= ~0x3;
+	DMIBAR32(0x88) |= 0x3;
+	reg16 = DMIBAR16(0x88);
+}
+
+/*
 	DMIBAR32(0x0028) = 0x00000001;
 	DMIBAR32(0x002c) = 0x86000000;
 	DMIBAR32(0x0040) = 0x08010005;
@@ -167,7 +293,7 @@ static void init_dmi(void)
 	EPBAR32(0x68) = 0x00008000;
 	EPBAR32(0x70) = 0x03000002;
 	EPBAR32(0x78) = 0x00030000;
-}
+*/
 
 void x4x_late_init(void)
 {