[coreboot-gerrit] Patch set updated for coreboot: intel/gma: Use defines for registers and values in edid.c

[Swift Geek (swiftgeek@gmail.com)]

Swift Geek (swiftgeek at gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16339

-gerrit

commit b923b9d051658f113f0f2ec031a08d92d7e49e67
Author: Swift Geek (Sebastian Grzywna) <swiftgeek at gmail.com>
Date:   Sat Aug 27 13:24:53 2016 +0200

    intel/gma: Use defines for registers and values in edid.c
    
    Replaces magic values with defines without changing any value.
    
    Change-Id: I332442045aa4a28ffed88fc52a99a4364684f00c
    Signed-off-by: Swift Geek (Sebastian Grzywna) <swiftgeek at gmail.com>
---
 src/drivers/intel/gma/edid.c | 54 ++++++++++++++++++++++++++++----------------
 1 file changed, 34 insertions(+), 20 deletions(-)

diff --git a/src/drivers/intel/gma/edid.c b/src/drivers/intel/gma/edid.c
index 9bde9b5..3902094 100644
--- a/src/drivers/intel/gma/edid.c
+++ b/src/drivers/intel/gma/edid.c
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2014 Vladimir Serbinenko <phcoder at gmail.com>
+ * Copyright (C) 2016 Sebastian Grzywna <swiftgeek at gmail.com>
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
@@ -20,13 +21,19 @@
 
 #include "i915_reg.h"
 #include "edid.h"
+#define GMBUS0_ADDR (mmio + 4 * 0)
+#define GMBUS1_ADDR (mmio + 4 * 1)
+#define GMBUS2_ADDR (mmio + 4 * 2)
+#define GMBUS3_ADDR (mmio + 4 * 3)
+#define GMBUS5_ADDR (mmio + 4 * 8)
+#define AT24_ADDR 0x50 /* EDID EEPROM */
 
 static void wait_rdy(u8 *mmio)
 {
 	unsigned try = 100;
 
 	while (try--) {
-		if (read32(mmio + 8) & (1 << 11))
+		if (read32(GMBUS2_ADDR) & GMBUS_HW_RDY)
 			return;
 		udelay(10);
 	}
@@ -35,19 +42,22 @@ static void wait_rdy(u8 *mmio)
 static void intel_gmbus_stop_bus(u8 * mmio, u8 bus)
 {
 	wait_rdy(mmio);
-	write32(mmio + 4 * 0, bus);
+	write32(GMBUS0_ADDR, bus);
 	wait_rdy(mmio);
-	write32(mmio + 4 * 8, 0);
-	write32(mmio + 4 * 1, 0x4e0400a1);
+	write32(GMBUS5_ADDR, 0);
+	write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
+		| GMBUS_CYCLE_STOP | ( 0x4 << GMBUS_BYTE_COUNT_SHIFT )
+		| GMBUS_SLAVE_READ | (AT24_ADDR << 1) );
 	wait_rdy(mmio);
-	write32(mmio + 4 * 8, 0);
-	write32(mmio + 4 * 1, 0x80000000);
-	write32(mmio + 4 * 1, 0x00000000);
+	write32(GMBUS5_ADDR, 0);
+	write32(GMBUS1_ADDR, GMBUS_SW_CLR_INT);
+	write32(GMBUS1_ADDR, 0);
 	wait_rdy(mmio);
-	write32(mmio + 4 * 1, 0x480000a0);
+	write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP | GMBUS_SLAVE_WRITE
+		| (AT24_ADDR << 1) );
 	wait_rdy(mmio);
-	write32(mmio + 4 * 0, 0x48000000);
-	write32(mmio + 4 * 2, 0x00008000);
+	write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP);
+	write32(GMBUS2_ADDR, GMBUS_INUSE);
 }
 
 void intel_gmbus_stop(u8 *mmio)
@@ -65,30 +75,34 @@ void intel_gmbus_read_edid(u8 *mmio, u8 bus, u8 slave, u8 *edid, u32 edid_size)
 
 	wait_rdy(mmio);
 	/* 100 KHz, hold 0ns,  */
-	write32(mmio + 4 * 0, bus);
+	write32(GMBUS0_ADDR, bus);
 	wait_rdy(mmio);
 	/* Ensure index bits are disabled.  */
-	write32(mmio + 4 * 8, 0);
-	write32(mmio + 4 * 1, 0x46000000 | (slave << 1));
+	write32(GMBUS5_ADDR, 0);
+	write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_INDEX
+		| (slave << 1) );
 	wait_rdy(mmio);
 	/* Ensure index bits are disabled.  */
-	write32(mmio + 4 * 8, 0);
-	write32(mmio + 4 * 1, 0x4a000001 | (slave << 1)
-		| (edid_size << 16));
+	write32(GMBUS5_ADDR, 0);
+	write32(GMBUS1_ADDR, GMBUS_SW_RDY | GMBUS_SLAVE_READ | GMBUS_CYCLE_WAIT
+		| GMBUS_CYCLE_STOP
+		| (edid_size << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
 	for (i = 0; i < edid_size / 4; i++) {
 		u32 reg32;
 		wait_rdy(mmio);
-		reg32 = read32(mmio + 4 * 3);
+		reg32 = read32(GMBUS3_ADDR);
 		edid[4 * i] = reg32 & 0xff;
 		edid[4 * i + 1] = (reg32 >> 8) & 0xff;
 		edid[4 * i + 2] = (reg32 >> 16) & 0xff;
 		edid[4 * i + 3] = (reg32 >> 24) & 0xff;
 	}
 	wait_rdy(mmio);
-	write32(mmio + 4 * 1, 0x4a800000 | (slave << 1));
+	write32(GMBUS1_ADDR, GMBUS_SW_RDY
+		| GMBUS_SLAVE_WRITE | GMBUS_CYCLE_WAIT | GMBUS_CYCLE_STOP
+		| (128 << GMBUS_BYTE_COUNT_SHIFT) | (slave << 1) );
 	wait_rdy(mmio);
-	write32(mmio + 4 * 0, 0x48000000);
-	write32(mmio + 4 * 2, 0x00008000);
+	write32(GMBUS0_ADDR, GMBUS_SW_RDY | GMBUS_CYCLE_STOP );
+	write32(GMBUS2_ADDR, GMBUS_INUSE);
 
 	printk (BIOS_SPEW, "EDID:\n");
 	for (i = 0; i < 128; i++) {