[coreboot-gerrit] Patch set updated for coreboot: mainboard/google/reef: drop remaining proto board references

[Aaron Durbin (adurbin@chromium.org)]

Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16432

-gerrit

commit 4d457c9e490947dc10f6d8c5dd8719bad4db4f88
Author: Aaron Durbin <adurbin at chromium.org>
Date:   Fri Sep 2 20:29:39 2016 -0500

    mainboard/google/reef: drop remaining proto board references
    
    The last vestige of the proto boards is the memory sku id
    gpios. No need for performing the memory sku read with pullups
    because all current and future boards don't have floating pins.
    
    BUG=chrome-os-partner:56791
    
    Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
    Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
 .../variants/baseboard/include/baseboard/gpio.h     |  6 +-----
 .../google/reef/variants/baseboard/memory.c         | 21 +--------------------
 2 files changed, 2 insertions(+), 25 deletions(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h
index 90cca36..f60bfdc 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/gpio.h
@@ -39,11 +39,7 @@
 #define GPIO_PCH_WP	GPIO_75
 #define GPIO_EC_IN_RW	GPIO_41
 
-/*
- * The proto boards didn't have memory SKU pins, but the same ones can be
- * utilized as post proto boards because the pins used were never connected
- * or no peripheral utilized the signals on proto boards.
- */
+/*  Memory SKU GPIOs. */
 #define MEM_CONFIG3	GPIO_45
 #define MEM_CONFIG2	GPIO_38
 #define MEM_CONFIG1	GPIO_102
diff --git a/src/mainboard/google/reef/variants/baseboard/memory.c b/src/mainboard/google/reef/variants/baseboard/memory.c
index a5b0364..b147253 100644
--- a/src/mainboard/google/reef/variants/baseboard/memory.c
+++ b/src/mainboard/google/reef/variants/baseboard/memory.c
@@ -62,14 +62,6 @@ const struct lpddr4_swizzle_cfg baseboard_lpddr4_swizzle = {
 	},
 };
 
-/*
- * Proto boards didn't have a memory SKU id. The configuration pins use
- * an internal weak pullup with stronger pulldowns for the 0 bits. As
- * proto boards didn't use the memory SKU pins the SKU id reads as 4'b1111,
- * i.e. 15.
- */
-#define PROTO_SKU 15
-
 static const struct lpddr4_sku skus[] = {
 	/*
 	 * K4F6E304HB-MGCJ - both logical channels While the parts
@@ -133,13 +125,6 @@ static const struct lpddr4_sku skus[] = {
 		.ch1_rank_density = LP4_8Gb_DENSITY,
 		.part_num = "H9HCNNN8KUMLHR",
 	},
-	/* K4F8E304HB-MGCH - both logical channels */
-	[PROTO_SKU] = {
-		.speed = LP4_SPEED_2400,
-		.ch0_rank_density = LP4_8Gb_DENSITY,
-		.ch1_rank_density = LP4_8Gb_DENSITY,
-		.part_num = "K4F8E304HB-MGCH",
-	},
 };
 
 static const struct lpddr4_cfg lp4cfg = {
@@ -160,9 +145,5 @@ size_t __attribute__((weak)) variant_memory_sku(void)
 		[1] = MEM_CONFIG1, [0] = MEM_CONFIG0,
 	};
 
-	/*
-	 * Read memory SKU id with internal pullups enabled to handle
-	 * proto boards with no SKU id pins.
-	 */
-	return gpio_pullup_base2_value(pads, ARRAY_SIZE(pads));
+	return gpio_base2_value(pads, ARRAY_SIZE(pads));
 }