[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cb

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com) gerrit at coreboot.org
Tue Sep 6 20:41:53 CEST 2016


Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16423

-gerrit

commit c23617b9031463624186888254a64497fab2f0b1
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date:   Fri Sep 2 16:04:27 2016 -0700

    soc/apollolake: Enable/disable Audio clk and power gate in devicetree.cb
    
    BUG=chrome-os-partner:56034
    
    Change-Id: Id88d262b32dea468536575117fc34d52076a3096
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
 src/soc/intel/apollolake/chip.c | 7 +++++++
 src/soc/intel/apollolake/chip.h | 7 +++++++
 2 files changed, 14 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 9cec08d..78c669d 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -400,6 +400,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 
 	/* Disable FSP from locking access to the RTC NVRAM */
 	silconfig->RtcLock = 0;
+
+	/* Enable Audio clk gate and power gate */
+	silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable;
+	silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable;
+	/* Bios config lockdown Audio clk and power gate */
+	silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown;
+
 }
 
 struct chip_operations soc_intel_apollolake_ops = {
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 22217a4..a9605b7 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -107,6 +107,13 @@ struct soc_intel_apollolake_config {
 	/* Enable DPTF support */
 	int dptf_enable;
 
+	/* Configure Audio clk gate and power gate
+	 * IOSF-SB port ID 92 offset 0x530 [5] and [3]
+	 */
+	uint8_t hdaudio_clk_gate_enable;
+	uint8_t hdaudio_pwr_gate_enable;
+	uint8_t hdaudio_bios_config_lockdown;
+
 	/* SLP S3 minimum assertion width. */
 	int slp_s3_assertion_width_usecs;
 };



More information about the coreboot-gerrit mailing list