[coreboot-gerrit] New patch to review for coreboot: Added onboard Spd data read with smbus

[Boon Tiong Teo (boon.tiong.teo@intel.com)]

Boon Tiong Teo (boon.tiong.teo at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16523

-gerrit

commit 766ab50864c881db2deaa5aabdb7d974d301f665
Author: bteo1 <boon.tiong.teo at intel.com>
Date:   Tue Sep 6 18:10:24 2016 +0800

    Added onboard Spd data read with smbus
    
    Change-Id: I9a5b6ee60179d73168f1b6caf4adbc709b9d524d
    Signed-off-by: bteo1 <boon.tiong.teo at intel.com>
---
 src/mainboard/intel/sklsdlbrk/spd/spd.c            | 27 ++++++++++++++++------
 src/mainboard/intel/sklsdlbrk/spd/spd.h            |  6 +++++
 src/soc/intel/skylake/include/fsp11/soc/romstage.h |  2 --
 src/soc/intel/skylake/include/soc/pei_data.h       |  2 ++
 4 files changed, 28 insertions(+), 9 deletions(-)

diff --git a/src/mainboard/intel/sklsdlbrk/spd/spd.c b/src/mainboard/intel/sklsdlbrk/spd/spd.c
index 02e5f18..03e3d3b 100644
--- a/src/mainboard/intel/sklsdlbrk/spd/spd.c
+++ b/src/mainboard/intel/sklsdlbrk/spd/spd.c
@@ -21,8 +21,21 @@
 #include <string.h>
 #include <soc/gpio.h>
 #include <soc/pei_data.h>
-#include <soc/romstage.h>
-#include <mainboard/intel/sklsdlbrk/spd/spd.h>
+#include <soc/smbus.h>
+#include <soc/iomap.h>
+#include "spd.h"
+
+/* smbus read byte */
+int smbus_rb(unsigned int device, unsigned int address)
+{
+	return do_smbus_read_byte(SMBUS_BASE_ADDRESS, device, address);
+}
+
+/* smbus write byte */
+int smbus_wb(unsigned int device, unsigned int address, unsigned int value)
+{
+	return do_smbus_write_byte(SMBUS_BASE_ADDRESS, device, address, value);
+}
 
 static void mainboard_print_spd_info(uint8_t spd[])
 {
@@ -74,7 +87,7 @@ static void mainboard_print_spd_info(uint8_t spd[])
 	if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) {
 		/* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */
 		printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n",
-		       capmb / 8 * busw / devw * ranks);
+			capmb / 8 * busw / devw * ranks);
 	}
 }
 
@@ -92,16 +105,16 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
 			saddr =
 				pei_data->spd_addresses[ch * 2 + dimm] >> 1;
 
-			smbus_write_byte(SPD_PAGE_ADDRESS_0 >> 1, 0, 0);
+			smbus_wb(SPD_PAGE_ADDRESS_0 >> 1, 0, 0);
 			for (i = 0; i < SPD_LEN / 2; i++)
 				pei_data->spd_data[ch][dimm][i] =
-					smbus_read_byte(saddr, i);
+					smbus_rb(saddr, i);
 
-			smbus_write_byte(SPD_PAGE_ADDRESS_1 >> 1, 0, 0);
+			smbus_wb(SPD_PAGE_ADDRESS_1 >> 1, 0, 0);
 
 			for (i = 256; i < SPD_LEN; i++)
 				pei_data->spd_data[ch][dimm][i] =
-					smbus_read_byte(saddr, i);
+					smbus_rb(saddr, i);
 
 			mainboard_print_spd_info(pei_data->spd_data[ch][dimm]);
 
diff --git a/src/mainboard/intel/sklsdlbrk/spd/spd.h b/src/mainboard/intel/sklsdlbrk/spd/spd.h
index dabcfe3..e460a7a 100644
--- a/src/mainboard/intel/sklsdlbrk/spd/spd.h
+++ b/src/mainboard/intel/sklsdlbrk/spd/spd.h
@@ -33,4 +33,10 @@
 #define SPD_PAGE_ADDRESS_0	0x6c
 #define SPD_PAGE_ADDRESS_1	0x6e
 
+/* smbus read byte */
+int smbus_rb(unsigned int device, unsigned int address);
+/* smbus write byte */
+int smbus_wb(unsigned int device, unsigned int address, unsigned int value);
+void mainboard_fill_spd_data(struct pei_data *pei_data);
+
 #endif /* _MAINBOARD_SPD_H_ */
diff --git a/src/soc/intel/skylake/include/fsp11/soc/romstage.h b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
index 6c40bd6..67a9bef 100644
--- a/src/soc/intel/skylake/include/fsp11/soc/romstage.h
+++ b/src/soc/intel/skylake/include/fsp11/soc/romstage.h
@@ -22,9 +22,7 @@
 void systemagent_early_init(void);
 void intel_early_me_status(void);
 void enable_smbus(void);
-int smbus_read_byte(unsigned device, unsigned address);
 
 int early_spi_read_wpsr(u8 *sr);
-void mainboard_fill_spd_data(struct pei_data *pei_data);
 
 #endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/skylake/include/soc/pei_data.h b/src/soc/intel/skylake/include/soc/pei_data.h
index be8ba79..dbb83ca 100644
--- a/src/soc/intel/skylake/include/soc/pei_data.h
+++ b/src/soc/intel/skylake/include/soc/pei_data.h
@@ -47,6 +47,8 @@ struct pei_data {
 	/* Console output function */
 	tx_byte_func tx_byte;
 
+	/* Set to 0 for memory down */
+	uint8_t spd_addresses[4];
 	/*
 	 * DIMM SPD data for memory down configurations
 	 * [CHANNEL][SLOT][SPD]