[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: Disable CLKREQ of unused PCIe root ports

[Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri@intel.com)]

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16557

-gerrit

commit 2d886055db39dad4f5cad997977f95b7823e8c6f
Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
Date:   Thu Sep 8 15:25:35 2016 -0700

    mainboard/google/reef: Disable CLKREQ of unused PCIe root ports
    
    1. Removes PCIe blocker for S0ix.
    2. Set the correct PCIe root port for wifi/bt on EVT.
    3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.
    
    Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
    Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri at intel.com>
---
 src/mainboard/google/reef/variants/baseboard/devicetree.cb | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 2ac20de..e663787 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -4,7 +4,14 @@ chip soc/intel/apollolake
 		device lapic 0 on end
 	end
 
-	register "pcie_rp4_clkreq_pin" = "0"    # wifi/bt
+	register "pcie_rp0_clkreq_pin" = "0"    # wifi/bt
+	# Disable unused clkreq of PCIe root ports
+	register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
+	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
+
 
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.