[coreboot-gerrit] New patch to review for coreboot: google/reef: Remove setting of GPIO_TIER1_SCI enable bit

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16566

-gerrit

commit baac0784f77750770e3c4a4382d9c1b11a68585b
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Sep 9 15:15:27 2016 -0700

    google/reef: Remove setting of GPIO_TIER1_SCI enable bit
    
    This patch removes setting of gpio_tier1_sci_en from mainboard
    smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
    now.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/mainboard/google/reef/smihandler.c | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/mainboard/google/reef/smihandler.c b/src/mainboard/google/reef/smihandler.c
index dbf9162..fe4f8c4 100644
--- a/src/mainboard/google/reef/smihandler.c
+++ b/src/mainboard/google/reef/smihandler.c
@@ -38,9 +38,6 @@ void mainboard_smi_sleep(u8 slp_typ)
 	pads = variant_sleep_gpio_table(&num);
 	gpio_configure_pads(pads, num);
 
-	if (slp_typ == ACPI_S3)
-		enable_gpe(GPIO_TIER_1_SCI);
-
 	if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
 		chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS,
 					MAINBOARD_EC_S5_WAKE_EVENTS);