[coreboot-gerrit] New patch to review for coreboot: [WIP]soc/apollolake: Restore MSRs after S3 resume

[Ravishankar Sarawadi (ravishankar.sarawadi@intel.com)]

Ravishankar Sarawadi (ravishankar.sarawadi at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16586

-gerrit

commit ae374f5934839c9376629503ab8f2adc6f2fcaa8
Author: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
Date:   Thu Sep 8 17:16:37 2016 -0700

    [WIP]soc/apollolake: Restore MSRs after S3 resume
    
    Restore necessary MSRs after suspend cycle.
    
    BUG=chrome-os-partner:56922
    BRANCH=None
    
    TEST=Check core/package MSRs using 'iotools'
    Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi at intel.com>
    
    Change-Id: I471252fdf2cbadc8e4203500d5854beee65f3131
---
 src/soc/intel/apollolake/cpu.c             | 24 +++++++++++++-
 src/soc/intel/apollolake/include/soc/msr.h | 50 ++++++++++++++++++++++++++++++
 2 files changed, 73 insertions(+), 1 deletion(-)

diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index 86fe3e1..72d35ab 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -25,11 +25,33 @@
 #include <cpu/x86/mtrr.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <reg_script.h>
 #include <soc/cpu.h>
+#include <soc/msr.h>
 #include <soc/smm.h>
 
+
+static const struct reg_script core_msr_script[] = {
+
+	REG_MSR_WRITE(MSR_PMG_CST_CONFIG_CONTROL, 0x8472),
+	REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, 0x50414),
+    /* Disable C1E */
+    REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0),
+    REG_SCRIPT_END
+};
+
+static void soc_core_init(device_t cpu)
+{
+    printk(BIOS_SPEW, "%s/%s ( %s )\n",
+            __FILE__, __func__, dev_name(cpu));
+    printk(BIOS_DEBUG, "Init Apollolake core.\n");
+
+    /* Set core MSRs */
+    reg_script_run(core_msr_script);
+}
+
 static struct device_operations cpu_dev_ops = {
-	.init = DEVICE_NOOP,
+	.init = soc_core_init,
 };
 
 static struct cpu_device_id cpu_table[] = {
diff --git a/src/soc/intel/apollolake/include/soc/msr.h b/src/soc/intel/apollolake/include/soc/msr.h
new file mode 100644
index 0000000..b2a318f
--- /dev/null
+++ b/src/soc/intel/apollolake/include/soc/msr.h
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_MSR_H_
+#define _SOC_MSR_H_
+
+#define MSR_IA32_PLATFORM_ID		0x17
+#define MSR_IA32_BIOS_SIGN_ID		0x8B
+#define MSR_BSEL_CR_OVERCLOCK_CONTROL	0xcd
+#define MSR_PLATFORM_INFO		0xce
+#define MSR_PMG_CST_CONFIG_CONTROL	0xe2
+#define MSR_PMG_IO_CAPTURE_BASE     0xe4
+#define		SINGLE_PCTL			(1 << 11)
+#define MSR_POWER_MISC			0x120
+#define		ENABLE_ULFM_AUTOCM_MASK		(1 << 2)
+#define		ENABLE_INDP_AUTOCM_MASK		(1 << 3)
+#define MSR_IA32_PERF_CTL		0x199
+#define MSR_IA32_MISC_ENABLES		0x1a0
+#define MSR_POWER_CTL			0x1fc
+#define MSR_PKG_POWER_SKU_UNIT		0x606
+#define MSR_PKG_POWER_LIMIT		0x610
+#define MSR_PP1_POWER_LIMIT		0x638
+#define MSR_IACORE_RATIOS		0x66a
+#define MSR_IACORE_TURBO_RATIOS		0x66c
+#define MSR_IACORE_VIDS			0x66b
+#define MSR_IACORE_TURBO_VIDS		0x66d
+#define MSR_PKG_TURBO_CFG1		0x670
+#define MSR_CPU_TURBO_WKLD_CFG1		0x671
+#define MSR_CPU_TURBO_WKLD_CFG2		0x672
+#define MSR_CPU_THERM_CFG1		0x673
+#define MSR_CPU_THERM_CFG2		0x674
+#define MSR_CPU_THERM_SENS_CFG		0x675
+
+/* Read BCLK from MSR */
+unsigned int cpu_bus_freq_khz(void);
+
+#endif /* _SOC_MSR_H_ */