[coreboot-gerrit] Patch set updated for coreboot: soc/apollolake: Set up GPIO_TIER1_SCI_EN properly

[Shaunak Saha (shaunak.saha@intel.com)]

Shaunak Saha (shaunak.saha at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16564

-gerrit

commit 13dcf1d3d238ff821be639756ed2cf8d06853ab5
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Sep 9 11:43:03 2016 -0700

    soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
    
    Currently we are setting the gpio_tier1_sci in smihandler before
    going to S3. But this won't work for S0iX as it happens from Linux
    kernel and SMI handler is not involved in that flow. We need to
    set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
    kernel before going to sleep checks what values are passed through
    ASL as wake events (through _PRW), keeps those enabled only and
    clears other bits in gpe0 enable registers. So we need to inform
    the kernel to keep gpio_tier_sci also set as these are needed for
    any wake event. This patch adds ASL code for sleep button device with
    HID id PNP0C0E. We are adding _PRW method for sleep button device
    with this patch.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
---
 src/soc/intel/apollolake/acpi/gpio.asl    | 13 +++++++++++++
 src/soc/intel/apollolake/include/soc/pm.h |  6 ------
 2 files changed, 13 insertions(+), 6 deletions(-)

diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl
index 03b8edd..f04cdf8 100644
--- a/src/soc/intel/apollolake/acpi/gpio.asl
+++ b/src/soc/intel/apollolake/acpi/gpio.asl
@@ -141,6 +141,19 @@ scope (\_SB) {
 			Return(0xf)
 		}
 	}
+
+	/*
+	 * Sleep button device ASL code. We are using this device to
+	 * add the _PRW method for a dummy wake event to kernel so that
+	 * before going to sleep kernel does not clear bit 15 in ACPI
+	 * gpe0a enable register which is actually the GPIO_TIER1_SCI_EN bit.
+	 */
+	Device (SLP)
+	{
+		Name (_HID, EisaId ("PNP0C0E"))
+
+		Name (_PRW, Package() { GPE0A_GPIO_TIER1_SCI_STS, 0x3 })
+	}
 }
 
 Scope(\_GPE)
diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h
index 3ee7403..2c12c8d 100644
--- a/src/soc/intel/apollolake/include/soc/pm.h
+++ b/src/soc/intel/apollolake/include/soc/pm.h
@@ -138,12 +138,6 @@
 #define   PCIE_GPE_EN		(1 << 9)
 #define   SWGPE_EN		(1 << 2)
 
-/*
- * Enables the setting of the GPIO_TIER1_SCI_STS bit to generate a wake event
- * and/or an SCI or SMI#.
- */
-#define GPIO_TIER_1_SCI		(1 << 15)
-
 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */
 #define PRSTS			0x1000
 #define GEN_PMCON1		0x1020