[coreboot-gerrit] Patch set updated for coreboot: soc/intel/apollolake: Update PL1 value in RAPL MMIO register

[Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com)]

Sumeet R Pawnikar (sumeet.r.pawnikar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16595

-gerrit

commit ab16aa0a4c82f8884c1b3e30d7d45fc8ae9c542c
Author: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
Date:   Tue Aug 23 11:20:20 2016 +0530

    soc/intel/apollolake: Update PL1 value in RAPL MMIO register
    
    Due to an incorrect value set for the power limit PL1, the
    system is not able to leverage full TDP capacity. FSP code
    sets the PL1 value as 6W in RAPL MMIO register based on
    fused soc tdp value. This RAPL MMIO register is a physically
    separate instance from RAPL MSR register. This patch sets
    PL1 value to 15W in RAPL MMIO register.
    
    BUG=chrome-os-partner:56524
    TEST=Built, booted on reef and verifed the package power
    with heavy workload.
    
    Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
    Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
 src/soc/intel/apollolake/chip.c                    | 22 ++++++++++++++++++++++
 src/soc/intel/apollolake/include/soc/cpu.h         |  1 +
 src/soc/intel/apollolake/include/soc/northbridge.h |  2 ++
 3 files changed, 25 insertions(+)

diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index 78c669d..69ee122 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -34,6 +34,7 @@
 #include <spi-generic.h>
 #include <soc/pm.h>
 #include <soc/p2sb.h>
+#include <soc/northbridge.h>
 
 #include "chip.h"
 
@@ -189,6 +190,24 @@ static void pcie_override_devicetree_after_silicon_init(void)
 	pcie_update_device_tree(PCIEB0_DEVFN, 2);
 }
 
+static void rapl_update(void)
+{
+	uint32_t *rapl_reg;
+	uint32_t val;
+	const uint32_t power_mw = 15000;
+
+	rapl_reg = (void*)(uintptr_t) (MCH_BASE_ADDR + MCHBAR_RAPL_PPL);
+
+	/* Due to an incorrect value set for the power limit PL1 as 6W in RAPL
+	 * MMIO register from FSP code, the system is not able to leverage full
+	 * TDP capacity. This RAPL MMIO register is a physically separate
+	 * instance from RAPL MSR register. Punit algorithm controls to the
+	 * minimum power limit PL1 mentioned in the RAPL MMIO and MSR registers.
+	 * Here, setting RAPL PL1 in Bits[14:0] to 15W in RAPL MMIO register. */
+	val = (power_mw << (rdmsr(MSR_PKG_POWER_SKU_UNIT).lo & 0xf)) / 1000;
+	write32(rapl_reg, (read32(rapl_reg) & ~0x7fff) | val);
+}
+
 static void soc_init(void *data)
 {
 	struct global_nvs_t *gnvs;
@@ -218,6 +237,9 @@ static void soc_init(void *data)
 
 	/* Allocate ACPI NVS in CBMEM */
 	gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
+
+	/* Update RAPL package power limit */
+	rapl_update();
 }
 
 static void soc_final(void *data)
diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h
index 8887c17..22412af 100644
--- a/src/soc/intel/apollolake/include/soc/cpu.h
+++ b/src/soc/intel/apollolake/include/soc/cpu.h
@@ -38,6 +38,7 @@ void apollolake_init_cpus(struct device *dev);
 #define   PREFETCH_L1_DISABLE	(1 << 0)
 #define   PREFETCH_L2_DISABLE	(1 << 2)
 
+#define MSR_PKG_POWER_SKU_UNIT	0x606
 
 #define MSR_L2_QOS_MASK(reg)		(0xd10 + reg)
 #define MSR_IA32_PQR_ASSOC		0xc8f
diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h
index 0f61674..04e369e 100644
--- a/src/soc/intel/apollolake/include/soc/northbridge.h
+++ b/src/soc/intel/apollolake/include/soc/northbridge.h
@@ -34,5 +34,7 @@
 #define MCH_IMR_PITCH		0x20
 #define MCH_NUM_IMRS		20
 
+/* RAPL Package Power Limit register under MCHBAR. */
+#define MCHBAR_RAPL_PPL		0x70A8
 
 #endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */