[coreboot-gerrit] New patch to review for coreboot: mainboard/google/reef: Configure PERST_0 pin

[Vaibhav Shankar (vaibhav.shankar@intel.com)]

Vaibhav Shankar (vaibhav.shankar at intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16603

-gerrit

commit c9a90bffb533b5ec5a4f6860e1212582544598fd
Author: Vaibhav Shankar <vaibhav.shankar at intel.com>
Date:   Wed Sep 14 10:39:29 2016 -0700

    mainboard/google/reef: Configure PERST_0 pin
    
    This configures PERST_0 in devicetree. For boards without
    PERST_0, the pin should be disabled. For boards with PERST_0
    the correct GPIO needs to be assigned.
    
    BUG=chrome-os-partner:55877
    
    Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
    Signed-off-by: Vaibhav Shankar <vaibhav.shankar at intel.com>
---
 src/mainboard/google/reef/variants/baseboard/devicetree.cb | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index f15260b..c83df61 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -12,6 +12,10 @@ chip soc/intel/apollolake
 	register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED"
 	register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED"
 
+	# GPIO for PERST_0
+	# If the Board has PERST_0 signal, assign the GPIO
+	# If the Board does not have PERST_0, assign GPIO_PRT0_UDEF
+	register "prt0_gpio" = "GPIO_PRT0_UDEF"
 
 	# EMMC TX DATA Delay 1
 	# Refer to EDS-Vol2-22.3.