[coreboot-gerrit] Patch set updated for coreboot: mainboard/reef: add variant support to ASL code
Aaron Durbin (adurbin@chromium.org)
gerrit at coreboot.org
Wed Sep 14 21:52:04 CEST 2016
Aaron Durbin (adurbin at chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16604
-gerrit
commit e586a5ea5ddea4de74c238636ee129a3a018c5e1
Author: Aaron Durbin <adurbin at chromium.org>
Date: Wed Sep 14 14:42:25 2016 -0500
mainboard/reef: add variant support to ASL code
There certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.
BUG=chrome-os-partner:56677
Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Signed-off-by: Aaron Durbin <adurbin at chromium.org>
---
src/mainboard/google/reef/acpi/dptf.asl | 94 ----------------------
src/mainboard/google/reef/acpi/ec.asl | 23 ------
src/mainboard/google/reef/acpi/mainboard.asl | 8 +-
src/mainboard/google/reef/acpi/superio.asl | 21 -----
src/mainboard/google/reef/dsdt.asl | 44 ++++++++--
.../baseboard/include/baseboard/acpi/dptf.asl | 89 ++++++++++++++++++++
.../reef/variants/baseboard/include/baseboard/ec.h | 14 ++++
.../variants/reef/include/variant/acpi/dptf.asl | 15 ++++
8 files changed, 162 insertions(+), 146 deletions(-)
diff --git a/src/mainboard/google/reef/acpi/dptf.asl b/src/mainboard/google/reef/acpi/dptf.asl
deleted file mode 100644
index 33d9b4d..0000000
--- a/src/mainboard/google/reef/acpi/dptf.asl
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define DPTF_CPU_PASSIVE 80
-#define DPTF_CPU_CRITICAL 90
-#define DPTF_CPU_ACTIVE_AC0 90
-#define DPTF_CPU_ACTIVE_AC1 80
-#define DPTF_CPU_ACTIVE_AC2 70
-#define DPTF_CPU_ACTIVE_AC3 60
-#define DPTF_CPU_ACTIVE_AC4 50
-
-#define DPTF_TSR0_SENSOR_ID 0
-#define DPTF_TSR0_SENSOR_NAME "Battery"
-#define DPTF_TSR0_PASSIVE 48
-#define DPTF_TSR0_CRITICAL 70
-
-#define DPTF_TSR1_SENSOR_ID 1
-#define DPTF_TSR1_SENSOR_NAME "Ambient"
-#define DPTF_TSR1_PASSIVE 60
-#define DPTF_TSR1_CRITICAL 70
-
-#define DPTF_TSR2_SENSOR_ID 2
-#define DPTF_TSR2_SENSOR_NAME "Charger"
-#define DPTF_TSR2_PASSIVE 55
-#define DPTF_TSR2_CRITICAL 100
-
-#define DPTF_ENABLE_CHARGER
-
-/* Charger performance states, board-specific values from charger and EC */
-Name (CHPS, Package () {
- Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
- Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
- Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
- Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
- Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
-})
-
-Name (DTRT, Package () {
- /* CPU Throttle Effect on CPU */
- Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 0 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
-
-#ifdef DPTF_ENABLE_CHARGER
- /* Charger Effect on Temp Sensor 1 */
- Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
-#endif
-
- /* CPU Effect on Temp Sensor 1 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
-
- /* CPU Effect on Temp Sensor 2 */
- Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
-})
-
-Name (MPPC, Package ()
-{
- 0x2, /* Revision */
- Package () { /* Power Limit 1 */
- 0, /* PowerLimitIndex, 0 for Power Limit 1 */
- 1600, /* PowerLimitMinimum */
- 15000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 200 /* StepSize */
- },
- Package () { /* Power Limit 2 */
- 1, /* PowerLimitIndex, 1 for Power Limit 2 */
- 6000, /* PowerLimitMinimum */
- 8000, /* PowerLimitMaximum */
- 1000, /* TimeWindowMinimum */
- 1000, /* TimeWindowMaximum */
- 1000 /* StepSize */
- }
-})
-
-/* Include soc specific DPTF changes */
-#include <soc/intel/apollolake/acpi/dptf.asl>
-/* Include common dptf ASL files */
-#include <soc/intel/common/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/reef/acpi/ec.asl b/src/mainboard/google/reef/acpi/ec.asl
deleted file mode 100644
index b70c070..0000000
--- a/src/mainboard/google/reef/acpi/ec.asl
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* Enable EC backed ALS device in ACPI */
-#define EC_ENABLE_ALS_DEVICE
-
-/* Enable EC backed PD MCU device in ACPI */
-#define EC_ENABLE_PD_MCU_DEVICE
-
-/* ACPI code for EC functions */
-#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl
index 0b2fdc8..e44f389 100644
--- a/src/mainboard/google/reef/acpi/mainboard.asl
+++ b/src/mainboard/google/reef/acpi/mainboard.asl
@@ -34,9 +34,11 @@ Scope (\_SB)
}
}
+/* Chrome OS Embedded Controller */
Scope (\_SB.PCI0.LPCB)
{
- /* Chrome OS Embedded Controller */
- #include "superio.asl"
- #include "ec.asl"
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
}
diff --git a/src/mainboard/google/reef/acpi/superio.asl b/src/mainboard/google/reef/acpi/superio.asl
deleted file mode 100644
index 555e2a2..0000000
--- a/src/mainboard/google/reef/acpi/superio.asl
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
-#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
-#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
-
-/* ACPI code for EC SuperIO functions */
-#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl
index 05876c0..3265941 100644
--- a/src/mainboard/google/reef/dsdt.asl
+++ b/src/mainboard/google/reef/dsdt.asl
@@ -13,6 +13,9 @@
* GNU General Public License for more details.
*/
+#include <variant/ec.h>
+#include <variant/gpio.h>
+
DefinitionBlock(
"dsdt.aml",
"DSDT",
@@ -43,11 +46,42 @@ DefinitionBlock(
/* Chipset specific sleep states */
#include <soc/intel/apollolake/acpi/sleepstates.asl>
- /* Mainboard Specific devices */
- #include "acpi/mainboard.asl"
+ /* LID and Power button. */
+ Scope (\_SB)
+ {
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Return (\_SB.PCI0.LPCB.EC0.LIDS)
+ }
+ Name (_PRW, Package () { GPE_EC_WAKE, 0x3 })
+ }
- Scope (\_SB) {
- /* Dynamic Platform Thermal Framework */
- #include "acpi/dptf.asl"
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ }
+ }
+
+ /* Chrome OS Embedded Controller */
+ Scope (\_SB.PCI0.LPCB)
+ {
+ /* ACPI code for EC SuperIO functions */
+ #include <ec/google/chromeec/acpi/superio.asl>
+ /* ACPI code for EC functions */
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ Scope (\_SB)
+ {
+ /* Per board variant specific definitions. */
+ #include <variant/acpi/dptf.asl>
+ /* Include soc specific DPTF changes */
+ #include <soc/intel/apollolake/acpi/dptf.asl>
+ /* Include common dptf ASL files */
+ #include <soc/intel/common/acpi/dptf/dptf.asl>
}
}
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
new file mode 100644
index 0000000..59527c2
--- /dev/null
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+#define DPTF_CPU_ACTIVE_AC0 90
+#define DPTF_CPU_ACTIVE_AC1 80
+#define DPTF_CPU_ACTIVE_AC2 70
+#define DPTF_CPU_ACTIVE_AC3 60
+#define DPTF_CPU_ACTIVE_AC4 50
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 100
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 1600, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 200 /* StepSize */
+ },
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 6000, /* PowerLimitMinimum */
+ 8000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 1000 /* StepSize */
+ }
+})
diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
index 542f33a..cebb81f 100644
--- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
+++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/ec.h
@@ -54,4 +54,18 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN)|\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+
#endif
diff --git a/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl
new file mode 100644
index 0000000..a69345d
--- /dev/null
+++ b/src/mainboard/google/reef/variants/reef/include/variant/acpi/dptf.asl
@@ -0,0 +1,15 @@
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/acpi/dptf.asl>
More information about the coreboot-gerrit
mailing list