[coreboot-gerrit] Patch merged into coreboot/master: soc/intel/skylake: Add FSP 2.0 support in romstage

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit 5bf42c6c23b462d9292e6854d3f334cf17e42825
Author: Barnali Sarkar <barnali.sarkar at intel.com>
Date:   Wed Aug 24 20:48:46 2016 +0530

    soc/intel/skylake: Add FSP 2.0 support in romstage
    
    Populate SoC related Memory initialization params.
    
    Post memory init, set DISB, setup stack and MTRRs using the postcar
    funtions provided in postcar_loader.c.
    
    TEST=Build and boot kunimitsu, dram initialization done.
    ramstage is loaded.
    
    Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
    Signed-off-by: Rizwan Qureshi <rizwan.qureshi at intel.com>
    Signed-off-by: Naresh G Solanki <naresh.solanki at intel.com>
    Reviewed-on: https://review.coreboot.org/16315
    Tested-by: build bot (Jenkins)
    Reviewed-by: Aaron Durbin <adurbin at chromium.org>


See https://review.coreboot.org/16315 for details.

-gerrit