[coreboot-gerrit] Patch merged into coreboot/master: soc/apollolake: Set up GPIO_TIER1_SCI_EN properly

[gerrit at coreboot.org]

the following patch was just integrated into master:
commit c8ae5995bb24006949dee02148c806e6de74aa2c
Author: Shaunak Saha <shaunak.saha at intel.com>
Date:   Fri Sep 9 11:43:03 2016 -0700

    soc/apollolake: Set up GPIO_TIER1_SCI_EN properly
    
    Currently we are setting the gpio_tier1_sci in smihandler before
    going to S3. But this won't work for S0iX as it happens from Linux
    kernel and SMI handler is not involved in that flow. We need to
    set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
    kernel before going to sleep checks what values are passed through
    ASL as wake events (through _PRW), keeps those enabled only and
    clears other bits in gpe0 enable registers. So we need to inform
    the kernel to keep gpio_tier_sci also set as these are needed for
    any wake event. This patch adds ASL code for sleep button device with
    HID id PNP0C0E. We are adding _PRW method for sleep button device
    with this patch.
    
    BUG=chrome-os-partner:56483
    TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
         Also from S0iX system is resuming for WIFI wake.
    
    Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
    Signed-off-by: Shaunak Saha <shaunak.saha at intel.com>
    Reviewed-on: https://review.coreboot.org/16564
    Tested-by: build bot (Jenkins)
    Reviewed-by: Duncan Laurie <dlaurie at chromium.org>


See https://review.coreboot.org/16564 for details.

-gerrit