[coreboot-gerrit] New patch to review for coreboot: northbridge/intel/fsp_sandybridge: Add space around operators

[HAOUAS Elyes (ehaouas@noos.fr)]

HAOUAS Elyes (ehaouas at noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16630

-gerrit

commit a48ea52e7f32ee370582c8d19792c789ffcdd463
Author: Elyes HAOUAS <ehaouas at noos.fr>
Date:   Sat Sep 17 20:43:41 2016 +0200

    northbridge/intel/fsp_sandybridge: Add space around operators
    
    Change-Id: I1b5cdfaf39be639a7ef71e66e91284fa186fbb86
    Signed-off-by: Elyes HAOUAS <ehaouas at noos.fr>
---
 src/northbridge/intel/fsp_sandybridge/acpi.c                 | 2 +-
 src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl    | 2 +-
 src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 2 +-
 src/northbridge/intel/fsp_sandybridge/gma.c                  | 4 ++--
 src/northbridge/intel/fsp_sandybridge/northbridge.c          | 4 ++--
 src/northbridge/intel/fsp_sandybridge/udelay.c               | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/northbridge/intel/fsp_sandybridge/acpi.c b/src/northbridge/intel/fsp_sandybridge/acpi.c
index 4da5157..499d96f 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi.c
+++ b/src/northbridge/intel/fsp_sandybridge/acpi.c
@@ -41,7 +41,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
 	if (!dev)
 		return current;
 
-	pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
+	pciexbar_reg = pci_read_config32(dev, PCIEXBAR);
 
 	// MMCFG not supported or not enabled.
 	if (!(pciexbar_reg & (1 << 0)))
diff --git a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
index 90d1b1a..dfe5e25 100644
--- a/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
+++ b/src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl
@@ -134,7 +134,7 @@ Device (MCHC)
 	}
 
 	/*
-	 * Search CPU0 _PSS looking for control=arg0 and then
+	 * Search CPU0 _PSS looking for control = arg0 and then
 	 * return previous P-state entry number for new _PPC
 	 *
 	 * Format of _PSS:
diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
index 08c3b0c..888da8e 100644
--- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
+++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c
@@ -95,7 +95,7 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams,
 void ChipsetFspReturnPoint(EFI_STATUS Status,
 		VOID *HobListPtr)
 {
-	*(void **)CBMEM_FSP_HOB_PTR=HobListPtr;
+	*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
 	if (Status == 0xFFFFFFFF) {
 		hard_reset();
 	}
diff --git a/src/northbridge/intel/fsp_sandybridge/gma.c b/src/northbridge/intel/fsp_sandybridge/gma.c
index a33cafa..cda9e08 100644
--- a/src/northbridge/intel/fsp_sandybridge/gma.c
+++ b/src/northbridge/intel/fsp_sandybridge/gma.c
@@ -31,7 +31,7 @@
 
 u32 map_oprom_vendev(u32 vendev)
 {
-	u32 new_vendev=vendev;
+	u32 new_vendev = vendev;
 
 	switch (vendev) {
 	case 0x80860102:		/* GT1 Desktop */
@@ -41,7 +41,7 @@ u32 map_oprom_vendev(u32 vendev)
 	case 0x80860122:		/* GT2 Desktop >=1.3GHz */
 	case 0x80860126:		/* GT2 Mobile >=1.3GHz */
 	case 0x80860166:                /* IVB */
-		new_vendev=0x80860106;	/* GT1 Mobile */
+		new_vendev = 0x80860106;	/* GT1 Mobile */
 		break;
 	}
 
diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c
index 99d8fbb..42341d1 100644
--- a/src/northbridge/intel/fsp_sandybridge/northbridge.c
+++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c
@@ -105,8 +105,8 @@ static void add_fixed_resources(struct device *dev, int index)
 	mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
 
 	if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {
-		printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
-		       "size=0x%x\n", pcie_config_base, pcie_config_size);
+		printk(BIOS_DEBUG, "Adding PCIe config bar base = 0x%08x "
+		       "size = 0x%x\n", pcie_config_base, pcie_config_size);
 		resource = new_resource(dev, index++);
 		resource->base = (resource_t) pcie_config_base;
 		resource->size = (resource_t) pcie_config_size;
diff --git a/src/northbridge/intel/fsp_sandybridge/udelay.c b/src/northbridge/intel/fsp_sandybridge/udelay.c
index d482199..8f95595 100644
--- a/src/northbridge/intel/fsp_sandybridge/udelay.c
+++ b/src/northbridge/intel/fsp_sandybridge/udelay.c
@@ -19,7 +19,7 @@
 #include <cpu/x86/msr.h>
 
 /**
- * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK=100MHz
+ * Intel SandyBridge/IvyBridge CPUs always run the TSC at BCLK = 100MHz
  */
 
 void udelay(u32 us)